Microchip Technology Inc.
Principal Engineer - CAD (Physical Verification)
Microchip Technology Inc., Chandler, Arizona, United States, 85249
Overview
Join to apply for the
Principal Engineer - CAD (Physical Verification)
role at
Microchip Technology Inc. The CAD group at Microchip offers global support for multiple technology nodes and tools used in product development providing innovative solutions for the design community. The candidate will focus on flow development and support for back end physical verification. If you have a solid software background and are interested in supporting semiconductor chip design, this maybe the job for you. Expertise using Siemens Calibre and/or Cadence Pegasus DRC, LVS and PERC tools is paramount. Candidate should not only know how to run the tools and debug results, but also have strengths in developing the verification run decks and in automating flow/procedures. An overall strong understanding in both the digital and analog sides of design is important to be effective, since development and support work will span a variety of design styles. Additionally, both circuit/electrical and layout/physical knowledge is important. Responsibilities
Develop physical verification regression test cases to QA physical verification decks Support Layout and Design engineers with physical verification activities using verification tools such as Siemens Calibre, Cadence Pegasus, or Synopsys Hercules Utilize Knowledge of advanced EDA methods to support ESD, ERC, Voltage-Aware DRC, via doubling methodologies, etc. Work with Technology Development and Device Engineering to develop DRC rules, additional devices, and design for manufacturability checks Develop rule decks as needed to support flow Verify and enhance foundry rule decks Support remote sites worldwide with layout verification activities Support debug of physical verification issues Work as a member of team to develop flows to improve quality and reliability of devices Tasks
The Tasks This Candidate Will Be Assigned Depends On Their Experience. There Are Several Areas In Which We Are Shorthanded. Potential Task Assignments Would Include Building of regression test cases for several PDKs of various process technologies Supporting 4nm to 600nm PDKs from TSMC, Global Foundries, Vanguard, Dongbu, Magnachip, etc. Calibre/Pegasus PERC – several PDKs still require PERC setup. Requirements/Qualifications
Bachelors with 10+ years developing and supporting physical verification activities, or Masters with 7.5+ years developing and supporting physical verification activities In depth knowledge of Calibre DesignRev scripting Fluent with SVRF and TVF Accomplished at debugging PV issues with RVE, Vue or other EDA visualizer Familiar with customizing Calibre Interactive Skilled with Tcl/Tk, Perl, Python, and other programming languages, inside and outside of EDA tools Solid knowledge of layout rules and concepts, device identification concepts, and foundry rules Strong knowledge of Design for Manufacturing solutions affecting quality, reliability, and yield of designs Prefer extensive knowledge of Calibre/Pegasus/Hercules syntax and semantics, or similar layout verification tool Strong knowledge of Cadence Virtuoso and/or CalibreDRV Prefer Extraction, Reliability and Dynamic Noise related knowledge Excellent verbal and written communication and interpersonal skills Travel Time
0% - 25% Physical Attributes
Feeling, Handling, Hearing, Seeing, Works Alone, Works Around Others Physical Requirements
80% sitting, 10% standing, 10% walking, 100% inside Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law. For more information on applicable equal employment regulations, please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster. Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes. Seniority level
Mid-Senior level Employment type
Full-time Industries
Appliances, Electrical, and Electronics Manufacturing and Semiconductor Manufacturing
#J-18808-Ljbffr
Join to apply for the
Principal Engineer - CAD (Physical Verification)
role at
Microchip Technology Inc. The CAD group at Microchip offers global support for multiple technology nodes and tools used in product development providing innovative solutions for the design community. The candidate will focus on flow development and support for back end physical verification. If you have a solid software background and are interested in supporting semiconductor chip design, this maybe the job for you. Expertise using Siemens Calibre and/or Cadence Pegasus DRC, LVS and PERC tools is paramount. Candidate should not only know how to run the tools and debug results, but also have strengths in developing the verification run decks and in automating flow/procedures. An overall strong understanding in both the digital and analog sides of design is important to be effective, since development and support work will span a variety of design styles. Additionally, both circuit/electrical and layout/physical knowledge is important. Responsibilities
Develop physical verification regression test cases to QA physical verification decks Support Layout and Design engineers with physical verification activities using verification tools such as Siemens Calibre, Cadence Pegasus, or Synopsys Hercules Utilize Knowledge of advanced EDA methods to support ESD, ERC, Voltage-Aware DRC, via doubling methodologies, etc. Work with Technology Development and Device Engineering to develop DRC rules, additional devices, and design for manufacturability checks Develop rule decks as needed to support flow Verify and enhance foundry rule decks Support remote sites worldwide with layout verification activities Support debug of physical verification issues Work as a member of team to develop flows to improve quality and reliability of devices Tasks
The Tasks This Candidate Will Be Assigned Depends On Their Experience. There Are Several Areas In Which We Are Shorthanded. Potential Task Assignments Would Include Building of regression test cases for several PDKs of various process technologies Supporting 4nm to 600nm PDKs from TSMC, Global Foundries, Vanguard, Dongbu, Magnachip, etc. Calibre/Pegasus PERC – several PDKs still require PERC setup. Requirements/Qualifications
Bachelors with 10+ years developing and supporting physical verification activities, or Masters with 7.5+ years developing and supporting physical verification activities In depth knowledge of Calibre DesignRev scripting Fluent with SVRF and TVF Accomplished at debugging PV issues with RVE, Vue or other EDA visualizer Familiar with customizing Calibre Interactive Skilled with Tcl/Tk, Perl, Python, and other programming languages, inside and outside of EDA tools Solid knowledge of layout rules and concepts, device identification concepts, and foundry rules Strong knowledge of Design for Manufacturing solutions affecting quality, reliability, and yield of designs Prefer extensive knowledge of Calibre/Pegasus/Hercules syntax and semantics, or similar layout verification tool Strong knowledge of Cadence Virtuoso and/or CalibreDRV Prefer Extraction, Reliability and Dynamic Noise related knowledge Excellent verbal and written communication and interpersonal skills Travel Time
0% - 25% Physical Attributes
Feeling, Handling, Hearing, Seeing, Works Alone, Works Around Others Physical Requirements
80% sitting, 10% standing, 10% walking, 100% inside Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law. For more information on applicable equal employment regulations, please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster. Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes. Seniority level
Mid-Senior level Employment type
Full-time Industries
Appliances, Electrical, and Electronics Manufacturing and Semiconductor Manufacturing
#J-18808-Ljbffr