Cynet systems Inc
Job Description:
Essential Functions:
Derive FPGA design specifications from system requirements.
Develop detailed FPGA architecture for implementation.
Implement design in RTL (VHDL) and perform module level simulations.
Perform Synthesis, Place and Route (PAR) and Static Timing Analysis (STA).
Perform RTL quality using: Lint, Reset Domain Crossing (RDC), Clock Domain Crossing (CDC) , Static Formal EDA.
Generate verification test plans and perform End to End Simulations.
Support Board, FPGA bring up.
Validate design through HW/SW integration test with test equipment.
Support product collateral for NSA certification.
Qualifications:
Bachelor of Science (BS) -Four year degree or Masters (MS) or PhD from an accredited course of study in engineering, engineering technology (chemistry, physics, mathematics, data science, or Electrical/Electronics/Computer Engineering/Computer Science).
3-5+ years’ experience designing FPGA products with VHDL.
Experience with Xilinx FPGAs and Vivado.
Experience with Revision control system.
Experience with Earned Value Management (EVM).
Good written, verbal, and presentation skills.
Active DoD Security Clearance.
Preferred Additional Skills:
Experience with mapping algorithms to architecture.
Experience in C++ (OOP).
Experience with any of protocols: Ethernet, TCP/IP, PCIe, NVMe, USB.
Experience with Xilinx SoC design with SDKs and PetaLinux OS.
Experience with High-Level Synthesis (HLS) with Vivado HLX or Mentor Catapu.
Must- Haves (Hard Skills):
Experience with Xilinx FPGAs and Vivado.
Experience with Revision control system.
Experience with Earned Value Management (EVM).
4-6 years of minimum experience with VHDL experience.
Extensive FPGA design going through design and verification process.
Ethernet framing and protocol experience in FPG.
Active Secret Clerance.
Good written, verbal, and presentation skills.
Nice-To- Haves (Hard Skills):
Experience with mapping algorithms to architecture.
Experience in C++ (OOP).
Experience with any of protocols : Ethernet, TCP/IP, PCIe, NVMe, USB.
Experience with Xilinx SoC design with SDKs and PetaLinux OS.
Experience with High-Level Synthesis (HLS) with Vivado HLX or Mentor Catapult.
Deal Breakers (Would not Consider).
Same manager/position as the Camden FPGA design engineer, please do not submit candidates that were reviewed and rejected for that one.
100% onsite.
Active Secret Clearance required.
Degree/Certification Requirements:
Bachelor of Science (BS) -Four year degree or Masters (MS) or PhD from an accredited course of study in engineering, engineering technology (chemistry, physics, mathematics, data science, or Electrical/Electronics/Computer Engineering/Computer Science).
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Derive FPGA design specifications from system requirements.
Develop detailed FPGA architecture for implementation.
Implement design in RTL (VHDL) and perform module level simulations.
Perform Synthesis, Place and Route (PAR) and Static Timing Analysis (STA).
Perform RTL quality using: Lint, Reset Domain Crossing (RDC), Clock Domain Crossing (CDC) , Static Formal EDA.
Generate verification test plans and perform End to End Simulations.
Support Board, FPGA bring up.
Validate design through HW/SW integration test with test equipment.
Support product collateral for NSA certification.
Qualifications:
Bachelor of Science (BS) -Four year degree or Masters (MS) or PhD from an accredited course of study in engineering, engineering technology (chemistry, physics, mathematics, data science, or Electrical/Electronics/Computer Engineering/Computer Science).
3-5+ years’ experience designing FPGA products with VHDL.
Experience with Xilinx FPGAs and Vivado.
Experience with Revision control system.
Experience with Earned Value Management (EVM).
Good written, verbal, and presentation skills.
Active DoD Security Clearance.
Preferred Additional Skills:
Experience with mapping algorithms to architecture.
Experience in C++ (OOP).
Experience with any of protocols: Ethernet, TCP/IP, PCIe, NVMe, USB.
Experience with Xilinx SoC design with SDKs and PetaLinux OS.
Experience with High-Level Synthesis (HLS) with Vivado HLX or Mentor Catapu.
Must- Haves (Hard Skills):
Experience with Xilinx FPGAs and Vivado.
Experience with Revision control system.
Experience with Earned Value Management (EVM).
4-6 years of minimum experience with VHDL experience.
Extensive FPGA design going through design and verification process.
Ethernet framing and protocol experience in FPG.
Active Secret Clerance.
Good written, verbal, and presentation skills.
Nice-To- Haves (Hard Skills):
Experience with mapping algorithms to architecture.
Experience in C++ (OOP).
Experience with any of protocols : Ethernet, TCP/IP, PCIe, NVMe, USB.
Experience with Xilinx SoC design with SDKs and PetaLinux OS.
Experience with High-Level Synthesis (HLS) with Vivado HLX or Mentor Catapult.
Deal Breakers (Would not Consider).
Same manager/position as the Camden FPGA design engineer, please do not submit candidates that were reviewed and rejected for that one.
100% onsite.
Active Secret Clearance required.
Degree/Certification Requirements:
Bachelor of Science (BS) -Four year degree or Masters (MS) or PhD from an accredited course of study in engineering, engineering technology (chemistry, physics, mathematics, data science, or Electrical/Electronics/Computer Engineering/Computer Science).
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