Arteris
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Senior Staff Design Verification Engineer (Ref #: 00066580) (Arteris, Inc. dba Arteris IP; Austin TX): Advanced UVM based test bench development and debugging. Defining, documenting, developing, and executing RTL verification test and coverage at system level. Performance verification and power-aware verification. Triaging Regressions, Debugging RTL designs in Verilog and System Verilog. Help improve and refine verification process, methodology, and metrics. UVM expertise on complex SoC projects from test bench development to verification closure. Provide technical guidance to Junior engineers and contractors in the development Online Advertisements
Senior Staff Design Verification Engineer (Ref #: 00066580) (Arteris, Inc. dba Arteris IP; Austin TX): Advanced UVM based test bench development and debugging. Defining, documenting, developing, and executing RTL verification test and coverage at system level. Performance verification and power-aware verification. Triaging Regressions, Debugging RTL designs in Verilog and System Verilog. Help improve and refine verification process, methodology, and metrics. UVM expertise on complex SoC projects from test bench development to verification closure. Provide technical guidance to Junior engineers and contractors in the development
process of testbench. Organize progress meetings with Junior engineers and contractions in the development process. Review testbench code and able to identify holes and improvements. Responsible for sub-system level verification tasks which are higher level than block level. Communicate and co-ordinate development tasks with peer teams like Software and Application Engineering teams. Partial remote work permitted with direct reporting to 9601 Amberglen Blvd. Suite 117 Austin, TX 78729.
Salary: $165,000 - $210,000 per year
Apply online at www.arteris.com/careers/open-positions/?p=apply Must include Ref #: 00066580. Seniority level
Seniority level Mid-Senior level Employment type
Employment type Full-time Job function
Job function Engineering and Information Technology Industries Semiconductor Manufacturing Referrals increase your chances of interviewing at Arteris by 2x Sign in to set job alerts for “Senior Design Verification Engineer” roles.
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Senior Staff Design Verification Engineer (Ref #: 00066580) (Arteris, Inc. dba Arteris IP; Austin TX): Advanced UVM based test bench development and debugging. Defining, documenting, developing, and executing RTL verification test and coverage at system level. Performance verification and power-aware verification. Triaging Regressions, Debugging RTL designs in Verilog and System Verilog. Help improve and refine verification process, methodology, and metrics. UVM expertise on complex SoC projects from test bench development to verification closure. Provide technical guidance to Junior engineers and contractors in the development Online Advertisements
Senior Staff Design Verification Engineer (Ref #: 00066580) (Arteris, Inc. dba Arteris IP; Austin TX): Advanced UVM based test bench development and debugging. Defining, documenting, developing, and executing RTL verification test and coverage at system level. Performance verification and power-aware verification. Triaging Regressions, Debugging RTL designs in Verilog and System Verilog. Help improve and refine verification process, methodology, and metrics. UVM expertise on complex SoC projects from test bench development to verification closure. Provide technical guidance to Junior engineers and contractors in the development
process of testbench. Organize progress meetings with Junior engineers and contractions in the development process. Review testbench code and able to identify holes and improvements. Responsible for sub-system level verification tasks which are higher level than block level. Communicate and co-ordinate development tasks with peer teams like Software and Application Engineering teams. Partial remote work permitted with direct reporting to 9601 Amberglen Blvd. Suite 117 Austin, TX 78729.
Salary: $165,000 - $210,000 per year
Apply online at www.arteris.com/careers/open-positions/?p=apply Must include Ref #: 00066580. Seniority level
Seniority level Mid-Senior level Employment type
Employment type Full-time Job function
Job function Engineering and Information Technology Industries Semiconductor Manufacturing Referrals increase your chances of interviewing at Arteris by 2x Sign in to set job alerts for “Senior Design Verification Engineer” roles.
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Austin, TX $136,000.00-$264,500.00 1 week ago Austin, TX $129,800.00-$212,800.00 1 week ago Austin, TX $129,800.00-$212,800.00 2 days ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
#J-18808-Ljbffr