ASIC Packet Processing Architect

Piper Companies is seeking a Packet Processor Architect to join a fast-growing innovator in AI infrastructure, for an onsite permanent position in Saratoga, CA . The Packet Processor Architect will design and lead the development of high-performance packet processing hardware that powers fast, intelligent data movement across complex network systems. Responsibilities of the Packet Processor Architect include: Architect scalable packet processing pipelines including classification, switching, routing, tunneling protocols (e.g., VxLAN, GRE), and congestion control features for high-performance networking ASICs Translate high-level requirements and use cases into detailed architectural and functional specifications while collaborating across hardware, firmware, and software teams Lead design validation and modeling of packet flow behavior across L2–L4, optimizing for throughput, latency, area, and power efficiency Drive IP integration and architectural decisions, including lookup optimizations, memory architecture, resource allocation, and support for programmable datapaths Support full development lifecycle, from design reviews to post-silicon tuning, performance debugging, and protocol compliance validation Qualifications for the Packet Processor Architect include: 15+ years of experience in networking or data-path ASIC architecture and design, with a proven track record in architecting packet-processing engines in high-throughput ASICs or SoCs Design and define microarchitecture for packet processing pipelines, including programmable datapaths, parser/deparser logic, hash function optimization, and efficient lookup structures Lead performance modeling and architectural trade-off analyses, balancing throughput, latency, area, and power across the ASIC lifecycle Oversee system-level integration of high-speed interfaces and IP blocks (e.g., PCIe, DMA, SerDes), ensuring alignment with physical design constraints and product goals Troubleshoot and resolve complex packet processing issues, applying deep protocol knowledge and cross-functional collaboration to deliver robust networking solutions Compensation for the Packet Processor Architect: Salary Range:

$280,000-$300,000/year Comprehensive Benefits:

Medical, Dental, Vision, sick leave if required by law, and 401K Keywords: ASIC architecture, packet processing pipelines, hardware network protocols, RTL design, Verilog, SystemVerilog, high-speed networking, protocol offload engines, Network-on-chip, P4, programmable data planes, HBM, DDR, SRAM, TCP/IP, RoCE, NVMe-of, load balancing, QoS, NFV, L2 switching, L3 switching, L4 switching, routing, MACsec, ethernet MAC/PHY integration. This job opens for applications on 8/15/25. Applications for this job will be accepted for at least 30 days from the posting date.

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