Rivos Inc.
Senior Member of Technical Staff | #93121
Join to apply for the
Senior Member of Technical Staff | #93121
role at
Rivos Inc. Senior Member of Technical Staff | #93121
1 month ago Be among the first 25 applicants Join to apply for the
Senior Member of Technical Staff | #93121
role at
Rivos Inc. Own the implementation of block level subcomponents and their physical integration into the
top level of a system-on-a-chip (SoC). The design cycle will start with synthesis of various
hierarchies to translate a High Level Description Language view of the functionality (Verilog
RTL) into a Gate Level Description (Verilog netlist). Take the netlist through the various steps
of a Place and Route flow (PnR) to produce manufacturable database (GDS) that meet all the
requirements of performance, power, and area specifications of the final product. Optimize floor
plans to integrate intellectual property cores and subsystems from internal groups and external
partners to achieve the smallest footprint area while satisfying all electrical integrity
requirements. Generate physical and timing constraints for sub-block implementation. Design,
implement, and analyze high frequency clock distribution networks at the top and block level to
enable communication between synchronous elements. Design, implement, and analyze high
performance interfaces between subsystems of the SoC for high speed communication. Analyze
and close timing by implementing design changes and fine-tuning of critical timing paths to
ensure the part operates at the target frequency. Run physical verification and implement fixes
to satisfy the design rules established by the chip foundry. Contribute to the automation of the
PnR flow by writing code in industry standard scripting languages to add customization and
collect metrics.
Education
Master’s or foreign equivalent in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field
Experience
3 years of experience in job offered or related occupation.
Special Requirements: Must have at least 1 year of prior work experience in each of the following
Owned partitions/blocks of a E-core CPU and took it through the various steps of a Place and Route flow (PnR) to produce manufacturable database (GDS) that meet all the requirements of performance, power, and area specifications of the final product. Analyzing and closing timing by implementing design changes and fine-tuning of critical timing paths to ensure the part operates at the target frequency. Optimizing floor plans to achieve the smallest footprint area of a given block (2M+ to 4M+ gates) while satisfying all electrical integrity requirements. Performing physical (pin placement) and timing constraints for sub-block implementation. Designing, analyzing and implementing high frequency clock distribution networks at the block level. Owning flow updates and contributing to the automation of the PnR flow by writing code in industry standard scripting languages to add customization and collect metrics. Working on full chip timing analysis and closure, including performing distributed timing analysis, ECO generation and timing model generation for hand off to SOC teams. Telecommuting allowed for this position**
$182,000 - $220,000 a year
Worksite:
6433 Champion Grandview Way
Building 2, Suite 150
Austin, Texas 78750
Applicant Instructions
Email resume to:
immigration@rivosinc.com .
Include job code 93121 in reply. EOE. Seniority level
Seniority level Mid-Senior level Employment type
Employment type Full-time Job function
Job function Engineering and Information Technology Industries Computer Hardware Manufacturing Referrals increase your chances of interviewing at Rivos Inc. by 2x Get notified about new Senior Member of Technical Staff jobs in
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#J-18808-Ljbffr
Join to apply for the
Senior Member of Technical Staff | #93121
role at
Rivos Inc. Senior Member of Technical Staff | #93121
1 month ago Be among the first 25 applicants Join to apply for the
Senior Member of Technical Staff | #93121
role at
Rivos Inc. Own the implementation of block level subcomponents and their physical integration into the
top level of a system-on-a-chip (SoC). The design cycle will start with synthesis of various
hierarchies to translate a High Level Description Language view of the functionality (Verilog
RTL) into a Gate Level Description (Verilog netlist). Take the netlist through the various steps
of a Place and Route flow (PnR) to produce manufacturable database (GDS) that meet all the
requirements of performance, power, and area specifications of the final product. Optimize floor
plans to integrate intellectual property cores and subsystems from internal groups and external
partners to achieve the smallest footprint area while satisfying all electrical integrity
requirements. Generate physical and timing constraints for sub-block implementation. Design,
implement, and analyze high frequency clock distribution networks at the top and block level to
enable communication between synchronous elements. Design, implement, and analyze high
performance interfaces between subsystems of the SoC for high speed communication. Analyze
and close timing by implementing design changes and fine-tuning of critical timing paths to
ensure the part operates at the target frequency. Run physical verification and implement fixes
to satisfy the design rules established by the chip foundry. Contribute to the automation of the
PnR flow by writing code in industry standard scripting languages to add customization and
collect metrics.
Education
Master’s or foreign equivalent in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field
Experience
3 years of experience in job offered or related occupation.
Special Requirements: Must have at least 1 year of prior work experience in each of the following
Owned partitions/blocks of a E-core CPU and took it through the various steps of a Place and Route flow (PnR) to produce manufacturable database (GDS) that meet all the requirements of performance, power, and area specifications of the final product. Analyzing and closing timing by implementing design changes and fine-tuning of critical timing paths to ensure the part operates at the target frequency. Optimizing floor plans to achieve the smallest footprint area of a given block (2M+ to 4M+ gates) while satisfying all electrical integrity requirements. Performing physical (pin placement) and timing constraints for sub-block implementation. Designing, analyzing and implementing high frequency clock distribution networks at the block level. Owning flow updates and contributing to the automation of the PnR flow by writing code in industry standard scripting languages to add customization and collect metrics. Working on full chip timing analysis and closure, including performing distributed timing analysis, ECO generation and timing model generation for hand off to SOC teams. Telecommuting allowed for this position**
$182,000 - $220,000 a year
Worksite:
6433 Champion Grandview Way
Building 2, Suite 150
Austin, Texas 78750
Applicant Instructions
Email resume to:
immigration@rivosinc.com .
Include job code 93121 in reply. EOE. Seniority level
Seniority level Mid-Senior level Employment type
Employment type Full-time Job function
Job function Engineering and Information Technology Industries Computer Hardware Manufacturing Referrals increase your chances of interviewing at Rivos Inc. by 2x Get notified about new Senior Member of Technical Staff jobs in
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Principal Deep Learning Software Development Engineer - C++, GPU
Austin, TX $200,000.00-$300,000.00 3 weeks ago Austin, TX $195,000.00-$298,800.00 6 days ago Austin, TX $79,800.00-$178,100.00 2 weeks ago Austin, TX $79,800.00-$178,100.00 1 week ago Austin, TX $79,800.00-$178,100.00 6 days ago Austin, TX $79,800.00-$178,100.00 2 hours ago Austin, TX $79,800.00-$178,100.00 3 hours ago Austin, TX $79,800.00-$178,100.00 3 hours ago Austin, TX $79,800.00-$178,100.00 2 hours ago Austin, TX $79,800.00-$178,100.00 6 days ago Austin, TX $79,800.00-$178,100.00 2 weeks ago Senior Principal Member of Technical Staff
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Austin, TX $96,800.00-$251,600.00 1 day ago Senior Member of Technical Staff (JoinOCI-SDE)
Austin, TX $96,800.00-$223,400.00 2 hours ago Austin, TX $96,800.00-$223,400.00 1 week ago Austin, TX $96,800.00-$223,400.00 3 hours ago Austin, TX $96,800.00-$223,400.00 1 week ago Austin, TX $96,800.00-$223,400.00 1 week ago Austin, TX $96,800.00-$223,400.00 2 weeks ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
#J-18808-Ljbffr