Xcelerium
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Xcelerium is a fabless semiconductor company developing advanced edge processors that bring AI processing to high-bandwidth sensors and wireless devices, unlocking hidden insights from every RF signal.
Working at Xcelerium will provide an opportunity to work on a complex development from the ground up and become familiar with cutting edge technologies such as wireless signal processing, computer vision, sensor fusion, machine learning and the opportunity to create and implement ground-up the latest VLSI methodologies with a collaborative, innovative team. In addition, the application domains will be 5G, UAVs / Drone, Robots, and Autonomous Vehicles which provide enormous scope for growth and making an impact.
ABOUT THE JOB
As a Senior Design Verification (DV) Engineer, you will play a pivotal role in the verification of Xcelerium's innovative RF sensing and communications SoCs, based on the industry-leading Edge Processing Unit (EPU). You will be responsible for end-to-end DV activities, including unit-level, integration-level, and SoC-level verification. You will work closely with RTL design engineers and collaborate with other DV engineers to ensure "on-time quality and customer satisfaction" through robust and comprehensive verification of our EPU and SoC designs to, as part of the team, achieve customer, and thereby our, success. RESPONSIBILITIES
Design Verification Planning and Strategy
Develop detailed verification plans, including test strategies and coverage metrics, for RISC-V processor-based designs with customized RVV and other extensions. Define and implement scalable testbench architectures using SystemVerilog Testbench (SVTB). Testbench Development and Test Implementation
Architect and implement reusable testbenches for unit, integration, and SoC level verification. Develop constrained-random verification environments with functional coverage using advanced DV methodologies. Implement and execute native processor code verification, leveraging RISC-V assembly and C tests. Assertion and Formal Verification
Develop and verify assertions using formal verification techniques, including property checking. Perform functional and formal verification to validate the design against specifications. Coverage Closure and Debugging
Ensure functional and code coverage closure with comprehensive analysis and reporting. Debug RTL and testbench issues in collaboration with RTL design engineers. Optimize verification efficiency through the reuse of existing testbenches and tests. Collaboration and Communication
Work closely with RTL engineers and other DV and DFT engineers to ensure smooth integration and verification flow. Collaborate in an agile development environment, participating in design and verification reviews. QUALIFICATIONS
Education
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Experience
5+ years of experience in design verification of processors, preferably RISC-V. Proven track record in verification of complex processor architectures, including vector extensions and custom instructions. Experience with verification of high-bandwidth, low-power signal processing and AI processing designs is a plus. Technical Skills
Expertise in SystemVerilog Testbench (SVTB) development and UVM (Universal Verification Methodology). Strong knowledge of constrained-random verification with functional coverage. Hands-on experience with formal verification, including property checking and assertion development. Native processor code verification experience, including RISC-V assembly and C-based tests. Proficiency in debugging tools and simulators such as VCS, ModelSim, or QuestaSim. Familiarity with scripting languages (Python, Perl, or Shell scripts) for automation and verification flow. Soft Skills
Excellent problem-solving and debugging skills. Strong communication and teamwork abilities. Self-motivated, proactive, and able to work efficiently in a fast-paced startup environment. We provide competitive compensation package. Senior: Mid-Senior level Type: Full-time Location: Irvine, CA
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As a Senior Design Verification (DV) Engineer, you will play a pivotal role in the verification of Xcelerium's innovative RF sensing and communications SoCs, based on the industry-leading Edge Processing Unit (EPU). You will be responsible for end-to-end DV activities, including unit-level, integration-level, and SoC-level verification. You will work closely with RTL design engineers and collaborate with other DV engineers to ensure "on-time quality and customer satisfaction" through robust and comprehensive verification of our EPU and SoC designs to, as part of the team, achieve customer, and thereby our, success. RESPONSIBILITIES
Design Verification Planning and Strategy
Develop detailed verification plans, including test strategies and coverage metrics, for RISC-V processor-based designs with customized RVV and other extensions. Define and implement scalable testbench architectures using SystemVerilog Testbench (SVTB). Testbench Development and Test Implementation
Architect and implement reusable testbenches for unit, integration, and SoC level verification. Develop constrained-random verification environments with functional coverage using advanced DV methodologies. Implement and execute native processor code verification, leveraging RISC-V assembly and C tests. Assertion and Formal Verification
Develop and verify assertions using formal verification techniques, including property checking. Perform functional and formal verification to validate the design against specifications. Coverage Closure and Debugging
Ensure functional and code coverage closure with comprehensive analysis and reporting. Debug RTL and testbench issues in collaboration with RTL design engineers. Optimize verification efficiency through the reuse of existing testbenches and tests. Collaboration and Communication
Work closely with RTL engineers and other DV and DFT engineers to ensure smooth integration and verification flow. Collaborate in an agile development environment, participating in design and verification reviews. QUALIFICATIONS
Education
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Experience
5+ years of experience in design verification of processors, preferably RISC-V. Proven track record in verification of complex processor architectures, including vector extensions and custom instructions. Experience with verification of high-bandwidth, low-power signal processing and AI processing designs is a plus. Technical Skills
Expertise in SystemVerilog Testbench (SVTB) development and UVM (Universal Verification Methodology). Strong knowledge of constrained-random verification with functional coverage. Hands-on experience with formal verification, including property checking and assertion development. Native processor code verification experience, including RISC-V assembly and C-based tests. Proficiency in debugging tools and simulators such as VCS, ModelSim, or QuestaSim. Familiarity with scripting languages (Python, Perl, or Shell scripts) for automation and verification flow. Soft Skills
Excellent problem-solving and debugging skills. Strong communication and teamwork abilities. Self-motivated, proactive, and able to work efficiently in a fast-paced startup environment. We provide competitive compensation package. Senior: Mid-Senior level Type: Full-time Location: Irvine, CA
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