Qualcomm
Company
Qualcomm Technologies, Inc.
Job Area Engineering Group > ASICS Engineering
General Summary As a Design Engineer, you’ll play a critical role in shaping cutting‑edge digital designs. Your responsibilities will include:
Micro‑Architecture: Designing micro‑architecture for both simple and complex digital interface blocks.
RTL Development: Developing RTL (Register Transfer Level) code using industry best practices. This includes handling multi‑clock designs, high‑frequency requirements, low power, and low latency considerations while ensuring high performance.
Debugging and Post‑Silicon Bring‑Up: Troubleshooting and debugging issues during the development process and supporting post‑silicon bring‑up activities.
Documentation: Creating comprehensive design documentation to ensure clarity and maintainability.
Design Optimization: Optimizing designs for key metrics such as area, power, and performance.
Cross‑Functional Collaboration: Collaborating with cross‑functional teams, including DFT (Design for Testability), Implementation, Verification, Emulation, and Firmware teams.
Must be in San Diego full time, 5 days a week.
Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information.
U.S. citizenship and security clearance:
Must be a U.S. citizen and eligible to receive a U.S. Government security clearance.
Ideal Candidate Will Have
10+ years of work experience with RTL/FPGA design (Verilog, SystemVerilog), embedded system architecture and Verification.
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 10+ years of Hardware Engineering or related work experience, or Master's degree with similar experience, or Ph.D. in a related field.
Preferred Qualifications
Positive Attitude: Bring a fun-loving attitude and a passion for inclusively solving problems.
Experience: 10+ years of ASIC design experience.
RTL Expertise: System Verilog Design, Linting, CDC, Synthesis (FPGA and ASIC).
Testing: Building the test suites for design validation.
Emulation: Understanding of emulation and prototyping flows for the design and validation in lab.
Complex Digital Logic Design: Experience designing complex digital logic blocks and subsystems (CPU, GPU, DSP, always‑on systems, digital interfaces such as PCIe, UART, I2C, DDRx, SPI, USB).
ISA Familiarity: Knowledge of ISAs (Instruction Set Architectures) such as ARM THUMB or RISC‑V.
Processor/Microcontroller System Design: Understanding of processor or microcontroller system design.
Multi‑Power Domain and Multi‑Clock Domain Designs: Experience with designs spanning multiple power domains and clock domains.
Scripting/Automation Languages: Proficiency in scripting or automation languages like Python or Perl.
Industry Standard Digital Tools: Familiarity with state‑of‑the‑art industry‑standard digital design tools.
Challenges of Lower Node Technologies: Awareness of challenges faced when working with lower node technologies.
If you’re excited about pushing the boundaries of digital design and collaborating with diverse teams, we encourage you to apply!
Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
Ph.D. in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
Pay Range and Other Compensation & Benefits $192,000.00 - $288,000.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play.
EEO Employer Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected classification.
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
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Job Area Engineering Group > ASICS Engineering
General Summary As a Design Engineer, you’ll play a critical role in shaping cutting‑edge digital designs. Your responsibilities will include:
Micro‑Architecture: Designing micro‑architecture for both simple and complex digital interface blocks.
RTL Development: Developing RTL (Register Transfer Level) code using industry best practices. This includes handling multi‑clock designs, high‑frequency requirements, low power, and low latency considerations while ensuring high performance.
Debugging and Post‑Silicon Bring‑Up: Troubleshooting and debugging issues during the development process and supporting post‑silicon bring‑up activities.
Documentation: Creating comprehensive design documentation to ensure clarity and maintainability.
Design Optimization: Optimizing designs for key metrics such as area, power, and performance.
Cross‑Functional Collaboration: Collaborating with cross‑functional teams, including DFT (Design for Testability), Implementation, Verification, Emulation, and Firmware teams.
Must be in San Diego full time, 5 days a week.
Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information.
U.S. citizenship and security clearance:
Must be a U.S. citizen and eligible to receive a U.S. Government security clearance.
Ideal Candidate Will Have
10+ years of work experience with RTL/FPGA design (Verilog, SystemVerilog), embedded system architecture and Verification.
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 10+ years of Hardware Engineering or related work experience, or Master's degree with similar experience, or Ph.D. in a related field.
Preferred Qualifications
Positive Attitude: Bring a fun-loving attitude and a passion for inclusively solving problems.
Experience: 10+ years of ASIC design experience.
RTL Expertise: System Verilog Design, Linting, CDC, Synthesis (FPGA and ASIC).
Testing: Building the test suites for design validation.
Emulation: Understanding of emulation and prototyping flows for the design and validation in lab.
Complex Digital Logic Design: Experience designing complex digital logic blocks and subsystems (CPU, GPU, DSP, always‑on systems, digital interfaces such as PCIe, UART, I2C, DDRx, SPI, USB).
ISA Familiarity: Knowledge of ISAs (Instruction Set Architectures) such as ARM THUMB or RISC‑V.
Processor/Microcontroller System Design: Understanding of processor or microcontroller system design.
Multi‑Power Domain and Multi‑Clock Domain Designs: Experience with designs spanning multiple power domains and clock domains.
Scripting/Automation Languages: Proficiency in scripting or automation languages like Python or Perl.
Industry Standard Digital Tools: Familiarity with state‑of‑the‑art industry‑standard digital design tools.
Challenges of Lower Node Technologies: Awareness of challenges faced when working with lower node technologies.
If you’re excited about pushing the boundaries of digital design and collaborating with diverse teams, we encourage you to apply!
Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
Ph.D. in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
Pay Range and Other Compensation & Benefits $192,000.00 - $288,000.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play.
EEO Employer Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected classification.
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
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