Intellisoft Technologies
FPGA RTL Design Engineer – Board Debug, Intel & Quartus Expert
Intellisoft Technologies, Santa Clara, California, us, 95053
Senior Manager – Client Services | Delivering High-Impact Professional Services for Strategic Clients
Duration:
1 Year (Contract)
Experience:
6–12 Years
Base Pay Range $75.00/hr – $80.00/hr
Job Description We are seeking a highly skilled FPGA RTL Design Engineer with strong hands‑on experience in Quartus‑based FPGA design, Intel & Quartus, and board‑level debug. The ideal candidate will work on complex high‑speed and precision FPGA systems, taking designs from concept through implementation, bring‑up, and validation.
Key Responsibilities
Develop and implement FPGA RTL designs using Verilog/VHDL/SystemVerilog.
Target and optimize designs for Intel/Altera Quartus FPGA platforms.
Perform IP integration, verification, and debug at block and system level.
Conduct board bring‑up, power/clock validation, and signal integrity analysis.
Debug and validate FPGA designs using SignalTap, ChipScope, oscilloscopes, and logic analyzers.
Collaborate with hardware and system teams to ensure functional validation and performance optimization.
Required Skills
6–12 years of FPGA design experience.
Strong proficiency in RTL design and simulation (Verilog/VHDL/SystemVerilog).
Hands‑on experience with Quartus, Vivado, and related FPGA toolchains.
Expertise in Board Debug and Hardware Bring‑up.
Experience with lab tools (oscilloscope, logic analyzer, multimeter).
Excellent problem‑solving and communication skills.
Why Join Us This role offers the opportunity to work on cutting‑edge FPGA designs in a fast‑paced environment in Santa Clara, collaborating with top engineering teams driving next‑generation hardware innovations.
#J-18808-Ljbffr
1 Year (Contract)
Experience:
6–12 Years
Base Pay Range $75.00/hr – $80.00/hr
Job Description We are seeking a highly skilled FPGA RTL Design Engineer with strong hands‑on experience in Quartus‑based FPGA design, Intel & Quartus, and board‑level debug. The ideal candidate will work on complex high‑speed and precision FPGA systems, taking designs from concept through implementation, bring‑up, and validation.
Key Responsibilities
Develop and implement FPGA RTL designs using Verilog/VHDL/SystemVerilog.
Target and optimize designs for Intel/Altera Quartus FPGA platforms.
Perform IP integration, verification, and debug at block and system level.
Conduct board bring‑up, power/clock validation, and signal integrity analysis.
Debug and validate FPGA designs using SignalTap, ChipScope, oscilloscopes, and logic analyzers.
Collaborate with hardware and system teams to ensure functional validation and performance optimization.
Required Skills
6–12 years of FPGA design experience.
Strong proficiency in RTL design and simulation (Verilog/VHDL/SystemVerilog).
Hands‑on experience with Quartus, Vivado, and related FPGA toolchains.
Expertise in Board Debug and Hardware Bring‑up.
Experience with lab tools (oscilloscope, logic analyzer, multimeter).
Excellent problem‑solving and communication skills.
Why Join Us This role offers the opportunity to work on cutting‑edge FPGA designs in a fast‑paced environment in Santa Clara, collaborating with top engineering teams driving next‑generation hardware innovations.
#J-18808-Ljbffr