Dice
Signal Integrity (SI) and Power Integrity (PI) Engineer
Dice, San Jose, California, United States, 95199
Signal Integrity (SI) and Power Integrity (PI) Engineer
Role : Signal Integrity (SI) and Power Integrity (PI) Engineer
JD :
Signal Integrity Engineer should support high-speed interface development and validation. The engineer will work on state-of-the-art technologies such as
LPDDR5X, PCIe Gen7, and UCIe (64G) .
Responsibilities:
Perform
channel modeling, extractions, and eye analysis
for high-speed interfaces.
Conduct
pre- and post-layout simulations
to ensure compliance with interface standards.
Analyze
crosstalk, reflections, jitter, and insertion/return loss .
Perform
power integrity extractions and simulations
for high-speed interfaces.
Model and analyze
package/board PDN
Define decoupling strategy and validate against system requirements.
Collaborate with design, package, and PCB teams to optimize SI performance.
Generate reports and recommendations to support design decisions.
Provide design guidelines balancing both
SI and PI constraints .
Qualifications:
Strong background in
both signal and power integrity .
Hands-on experience with SI tools (listed above).
Proficiency with
PI extraction/simulation tools
(e.g., PowerSI, SIwave, AEDT, HSPICE, equivalent).
Knowledge of DDR, PCIe, UCIe standards and PDN design best practices.
Familiarity with JEDEC/LPDDR5/6 and PCIe/UCIe standards.
Strong problem-solving skills and ability to work across cross-functional teams.
Strong analytical and communication skills.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
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JD :
Signal Integrity Engineer should support high-speed interface development and validation. The engineer will work on state-of-the-art technologies such as
LPDDR5X, PCIe Gen7, and UCIe (64G) .
Responsibilities:
Perform
channel modeling, extractions, and eye analysis
for high-speed interfaces.
Conduct
pre- and post-layout simulations
to ensure compliance with interface standards.
Analyze
crosstalk, reflections, jitter, and insertion/return loss .
Perform
power integrity extractions and simulations
for high-speed interfaces.
Model and analyze
package/board PDN
Define decoupling strategy and validate against system requirements.
Collaborate with design, package, and PCB teams to optimize SI performance.
Generate reports and recommendations to support design decisions.
Provide design guidelines balancing both
SI and PI constraints .
Qualifications:
Strong background in
both signal and power integrity .
Hands-on experience with SI tools (listed above).
Proficiency with
PI extraction/simulation tools
(e.g., PowerSI, SIwave, AEDT, HSPICE, equivalent).
Knowledge of DDR, PCIe, UCIe standards and PDN design best practices.
Familiarity with JEDEC/LPDDR5/6 and PCIe/UCIe standards.
Strong problem-solving skills and ability to work across cross-functional teams.
Strong analytical and communication skills.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
#J-18808-Ljbffr