Design-for-Test Engineer | ASIC / SoC | Austin

DFT Engineer – Next‑Gen AI and Cloud SoCs Location:

Austin, Texas (Onsite, 5 days/week)

Salary:

$170,000–$200,000 USD + Equity (4‑year vesting)

Visa:

H1‑B sponsorship available

Skills:

DFT Specification & Architecture, ATPG, MBIST, JTAG, Silicon Bring‑up & Test (ATE), Scan Chains, DFT Compression, Logic BIST, EDA Test Tools (DFT Max, Tessent, Modus, SpyGlass, Design/Fusion Compiler, TestKompress), IP Integration, ASIC Synthesis & Verification, Problem‑Solving, Communication

Experience:

5–8 years (DFT specialization required)

Must‑Haves

5+ years in DFT spec, architecture, insertion, and analysis for complex silicon

Experience in silicon bring‑up, debug/validation of DFT on ATE, ATPG, MBIST, JTAG

ASIC DFT, synthesis, simulation/verification know‑how

Strong organizational/problem‑solving skills; detail oriented

Willing to work on‑site in Austin, TX (Relocation not covered)

Preferred

Master’s degree in Electrical Engineering

IP integration (memories, test controllers, MBIST, TAP)

Expert use of EDA tools: DFT Max, Tessent, Modus, Design/Fusion Compiler, SpyGlass, TestKompress; Silicon test coverage improvement; hierarchical design/test

Responsibilities

Lead and implement SoC DFT architecture and ATPG/MBIST strategy

Insert, validate, and debug all DFT logic – scan chains, BIST, boundary scan, TAP, compression, MBIST

Own silicon bring‑up and ATE debug for new test features and DFT IP

Collaborate to improve test coverage, resolve RTL violations, and streamline test processes

Develop and maintain formal DFT documentation

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