Mogi I/O : OTT/Podcast/Short Video Apps for you
DFT Engineer | Semiconductor / SoC / AI Chips
Mogi I/O : OTT/Podcast/Short Video Apps for you, Austin, Texas, us, 78716
Overview
Well‑funded hardware startup (with $180 MM in recent funding, backed by leading VCs) seeks an experienced DFT Engineer to innovate and own design‑for‑test (DFT) methodologies for advanced digital and mixed‑signal SoCs. This hands‑on role collaborates cross‑functionally to define, implement, and deploy robust DFT strategies for next‑generation programmable DSP chips powering the world’s fastest AI and cloud infrastructure.
Location Austin, Texas (Onsite, 5 days/week)
Industry Semiconductor, AI Infrastructure, Cloud Hardware
Compensation $170,000–$200,000 USD + Equity (4‑year vesting)
Visa H1‑B sponsorship available
Job Type Full‑time
Experience 5–8 years (DFT specialization required)
Skills
DFT specification & architecture, ATPG, MBIST, JTAG, silicon bring‑up & test (ATE)
Scan chains, DFT compression, logic BIST, EDA test tools (DFT Max, Tessent, Modus, SpyGlass, Design/Fusion Compiler, TestKompress)
IP integration, ASIC synthesis & verification
Strong organizational, problem‑solving, and communication skills
Must‑Haves
5+ years in DFT spec, architecture, insertion, and analysis for complex silicon
Experience in silicon bring‑up, debug/validation of DFT on ATE, ATPG, MBIST, JTAG
ASIC DFT, synthesis, simulation/verification know‑how
Detail‑oriented, strong organizational/problem‑solving skills
Willing to work on‑site in Austin, TX (relocation not covered)
Preferred
Master’s degree in Electrical Engineering
IP integration (memories, test controllers, MBIST, TAP)
Expert use of EDA tools for silicon test coverage improvement and hierarchical design/test
Responsibilities
Lead and implement SoC DFT architecture and ATPG/MBIST strategy
Insert, validate, and debug all DFT logic – scan chains, BIST, boundary scan, TAP, compression, MBIST
Own silicon bring‑up and ATE debug for new test features and DFT IP
Collaborate to improve test coverage, resolve RTL violations, and streamline test processes
Develop and maintain formal DFT documentation
Seniority Level Mid‑Senior level
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Location Austin, Texas (Onsite, 5 days/week)
Industry Semiconductor, AI Infrastructure, Cloud Hardware
Compensation $170,000–$200,000 USD + Equity (4‑year vesting)
Visa H1‑B sponsorship available
Job Type Full‑time
Experience 5–8 years (DFT specialization required)
Skills
DFT specification & architecture, ATPG, MBIST, JTAG, silicon bring‑up & test (ATE)
Scan chains, DFT compression, logic BIST, EDA test tools (DFT Max, Tessent, Modus, SpyGlass, Design/Fusion Compiler, TestKompress)
IP integration, ASIC synthesis & verification
Strong organizational, problem‑solving, and communication skills
Must‑Haves
5+ years in DFT spec, architecture, insertion, and analysis for complex silicon
Experience in silicon bring‑up, debug/validation of DFT on ATE, ATPG, MBIST, JTAG
ASIC DFT, synthesis, simulation/verification know‑how
Detail‑oriented, strong organizational/problem‑solving skills
Willing to work on‑site in Austin, TX (relocation not covered)
Preferred
Master’s degree in Electrical Engineering
IP integration (memories, test controllers, MBIST, TAP)
Expert use of EDA tools for silicon test coverage improvement and hierarchical design/test
Responsibilities
Lead and implement SoC DFT architecture and ATPG/MBIST strategy
Insert, validate, and debug all DFT logic – scan chains, BIST, boundary scan, TAP, compression, MBIST
Own silicon bring‑up and ATE debug for new test features and DFT IP
Collaborate to improve test coverage, resolve RTL violations, and streamline test processes
Develop and maintain formal DFT documentation
Seniority Level Mid‑Senior level
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