Mogi I/O : OTT/Podcast/Short Video Apps for you
Test Development Engineer (DFT)
Mogi I/O : OTT/Podcast/Short Video Apps for you, Austin, Texas, us, 78716
Base pay: $170,000 – $200,000 USD + Equity (4‑year vesting)
Location: Austin, Texas (Onsite, 5 days/week)
Employment type: Full- time
Summary We’re a well‑funded hardware startup (with $180MM in recent funding, backed by leading VCs) seeking an experienced DFT Engineer to innovate and own design‑for‑test (DFT) methodologies for advanced digital and mixed‑signal SoCs powering the world’s fastest AI and cloud infrastructure. This hands‑on role collaborates cross‑functionally to define, implement, and deploy robust DFT strategies for next‑generation programmable DSP chips.
Must‑Haves
5+ years in DFT specification, architecture, insertion, and analysis for complex silicon.
Experience in silicon bring‑up, debug/validation of DFT on ATE, ATPG, MBIST, JTAG.
ASIC DFT, synthesis, simulation/verification expertise.
Strong organizational and problem‑solving skills; detail oriented.
Willing to work on‑site in Austin, TX (relocation not covered).
Preferred
Master’s degree in Electrical Engineering.
IP integration experience (memories, test controllers, MBIST, TAP).
Expertise with EDA tools: DFT Max, Tessent, Modus, Design/Fusion Compiler, SpyGlass, TestKompress.
Silicon test coverage improvement and hierarchical design/test.
Responsibilities
Lead and implement SoC DFT architecture and ATPG/MBIST strategy.
Insert, validate, and debug all DFT logic – scan chains, BIST, boundary scan, TAP, compression, MBIST.
Own silicon bring‑up and ATE debug for new test features and DFT IP.
Collaborate to improve test coverage, resolve RTL violations, and streamline test processes.
Develop and maintain formal DFT documentation.
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Location: Austin, Texas (Onsite, 5 days/week)
Employment type: Full- time
Summary We’re a well‑funded hardware startup (with $180MM in recent funding, backed by leading VCs) seeking an experienced DFT Engineer to innovate and own design‑for‑test (DFT) methodologies for advanced digital and mixed‑signal SoCs powering the world’s fastest AI and cloud infrastructure. This hands‑on role collaborates cross‑functionally to define, implement, and deploy robust DFT strategies for next‑generation programmable DSP chips.
Must‑Haves
5+ years in DFT specification, architecture, insertion, and analysis for complex silicon.
Experience in silicon bring‑up, debug/validation of DFT on ATE, ATPG, MBIST, JTAG.
ASIC DFT, synthesis, simulation/verification expertise.
Strong organizational and problem‑solving skills; detail oriented.
Willing to work on‑site in Austin, TX (relocation not covered).
Preferred
Master’s degree in Electrical Engineering.
IP integration experience (memories, test controllers, MBIST, TAP).
Expertise with EDA tools: DFT Max, Tessent, Modus, Design/Fusion Compiler, SpyGlass, TestKompress.
Silicon test coverage improvement and hierarchical design/test.
Responsibilities
Lead and implement SoC DFT architecture and ATPG/MBIST strategy.
Insert, validate, and debug all DFT logic – scan chains, BIST, boundary scan, TAP, compression, MBIST.
Own silicon bring‑up and ATE debug for new test features and DFT IP.
Collaborate to improve test coverage, resolve RTL violations, and streamline test processes.
Develop and maintain formal DFT documentation.
#J-18808-Ljbffr