Northrop Grumman Corp. (JP)
Staff Lead Design Verification Engineer
Northrop Grumman Corp. (JP), Baltimore, Maryland, United States
RELOCATION ASSISTANCE: Relocation assistance may be available
CLEARANCE TYPE: A US Government security clearance per customer's requirements.
TRAVEL: Yes, 10% of the Time
Description
At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work — and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history.
The Systems Engineering Integration & Test (SEIT) department is seeking a Staff Lead Design Verification Engineer to join our team and develop these technologies into high-performance computing systems that solve an assortment of unique mission needs. You’ll work in a fast-paced team environment alongside physicists, design engineers, and superconducting foundry engineers to make these technologies a reality.
What You'll Get To Do:
As a Digital Verification Lead Engineer, you will have an opportunity to be a part of a technology development organization that is collaborative, open, transparent, team-oriented, and flexible, where continuous learning is encouraged, all within a culture of design. We are seeking an exceptional Senior Functional Verification Engineer specializing in ASIC and FPGA technologies. The ideal candidate will play a critical role in behavioral simulation, and comprehensive functional verification processes.
Role And Responsibilities:
The Debug and Staff Lead Design Verification Engineer will be responsible leading the verification team for debug, emulation, and test development for state-of-the-art Digital Logic (High Speed Serial). Other responsibilities will include:
Design Entry & RTL Development:
Create comprehensive test-benches for behavioral simulation
Design and implement verification strategies for complex digital systems
Ensure RTL implementation meets precise design specification requirements
Functional Verification: Conduct in-depth behavioral simulations across ASIC and FPGA
Generate and execute advanced UVM Test cases
Achieve 95% code coverage goals and functional coverage across critical metrics
Perform detailed code coverage analysis, including: (Statement coverage, Expression coverage, Branch coverage, Toggle coverage)
Simulation: Utilize both functional and timing simulation tools
Verify logical behavior and implementation accuracy
Identify and resolve signal delay and performance issues in gate timing requirements
Develop comprehensive Universal Verification Methodology (UVM) simulation environments
Collaborative Processes: Work closely with design teams to validate RTL implementations
Provide detailed feedback and recommendations for design improvements
Participate in design reviews and Lead in verification planning
Mentor junior verification engineers
Contribute to continuous improvement of verification methodologies
This position is contingent upon clearance. This position will serve on-site in Linthicum/ Annapolis Junction, MD. Basic Qualifications For Staff Lead Design Verification Engineer: Bachelor's degree in Computer Engineering, BSEE, or comparable STEM Degree and 12 years industry experience in a design verification role or Master’s Degree plus 10 years experience or PhD plus 7 years experience
Experience with functional verification methodology for the full life cycle of products with leading a team with various levels of experience and skills
Demonstrated experience leading Verification Teams
Specialized experience in functional verification with multiple Tape Outs
Expert-level proficiency in Hardware Description Languages: (Verilog, VHDL, SystemVerilog)
Extensive knowledge of: (comprehensive RTL design methodologies, Behavioral simulation techniques, Code coverage strategies)
Extensive experience with industry-standard EDA tools (Cadence, Synopsys, Mentor Graphics)
Extensive experience with verification methodologies: Universal Verification Methodology (UVM)
Regression and automation framework development
This position requires the applicant to be a U.S. citizen
Candidates MUST HAVE an active TS/SCI clearance per business requirements.
Preferred Qualifications For Staff Lead Design Verification Engineer: Advanced Degrees in Electrical Engineering, Computer Engineering, Computer Science, or related technical fields
Experience with advanced Gate Level Simulations
Experience with the management of schedule, cost, metric reporting, and trade studies
Salary Range: $188,200.00 - $282,200.00 The above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as the scope and responsibilities of the position and the candidate's experience, education, skills and current market conditions. Depending on the position, employees may be eligible for overtime, shift differential, and a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives. In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business. The application period for the job is estimated to be 20 days from the job posting date. However, this timeline may be shortened or extended depending on business needs and the availability of qualified candidates. Northrop Grumman is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO and pay transparency statement, please visit http://www.northropgrumman.com/EEO. U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions.
#J-18808-Ljbffr
Design and implement verification strategies for complex digital systems
Ensure RTL implementation meets precise design specification requirements
Functional Verification: Conduct in-depth behavioral simulations across ASIC and FPGA
Generate and execute advanced UVM Test cases
Achieve 95% code coverage goals and functional coverage across critical metrics
Perform detailed code coverage analysis, including: (Statement coverage, Expression coverage, Branch coverage, Toggle coverage)
Simulation: Utilize both functional and timing simulation tools
Verify logical behavior and implementation accuracy
Identify and resolve signal delay and performance issues in gate timing requirements
Develop comprehensive Universal Verification Methodology (UVM) simulation environments
Collaborative Processes: Work closely with design teams to validate RTL implementations
Provide detailed feedback and recommendations for design improvements
Participate in design reviews and Lead in verification planning
Mentor junior verification engineers
Contribute to continuous improvement of verification methodologies
This position is contingent upon clearance. This position will serve on-site in Linthicum/ Annapolis Junction, MD. Basic Qualifications For Staff Lead Design Verification Engineer: Bachelor's degree in Computer Engineering, BSEE, or comparable STEM Degree and 12 years industry experience in a design verification role or Master’s Degree plus 10 years experience or PhD plus 7 years experience
Experience with functional verification methodology for the full life cycle of products with leading a team with various levels of experience and skills
Demonstrated experience leading Verification Teams
Specialized experience in functional verification with multiple Tape Outs
Expert-level proficiency in Hardware Description Languages: (Verilog, VHDL, SystemVerilog)
Extensive knowledge of: (comprehensive RTL design methodologies, Behavioral simulation techniques, Code coverage strategies)
Extensive experience with industry-standard EDA tools (Cadence, Synopsys, Mentor Graphics)
Extensive experience with verification methodologies: Universal Verification Methodology (UVM)
Regression and automation framework development
This position requires the applicant to be a U.S. citizen
Candidates MUST HAVE an active TS/SCI clearance per business requirements.
Preferred Qualifications For Staff Lead Design Verification Engineer: Advanced Degrees in Electrical Engineering, Computer Engineering, Computer Science, or related technical fields
Experience with advanced Gate Level Simulations
Experience with the management of schedule, cost, metric reporting, and trade studies
Salary Range: $188,200.00 - $282,200.00 The above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as the scope and responsibilities of the position and the candidate's experience, education, skills and current market conditions. Depending on the position, employees may be eligible for overtime, shift differential, and a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives. In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business. The application period for the job is estimated to be 20 days from the job posting date. However, this timeline may be shortened or extended depending on business needs and the availability of qualified candidates. Northrop Grumman is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO and pay transparency statement, please visit http://www.northropgrumman.com/EEO. U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions.
#J-18808-Ljbffr