Qualcomm
Senior Design Verification Engineer - QGOV
Qualcomm, San Diego, California, United States, 92189
Senior ASIC Design Verification Engineer - Lead
Company
Qualcomm Technologies, Inc.
Job Area
Engineering Group > ASICS Engineering
Role General Summary
Familiarity with RTL design in Verilog and System Verilog
Develop verification methodology, ensuring scalable and portable environment across simulation and emulation.
Develop test plan to verify Hardware building blocks, Design macros and Standard interfaces (PCIE, DDR, USB, I2C, SPI, etc)
Own end to end DV tasks from coding Test bench and test cases, write assertions, running simulations and achieving all coverage goals
Explore innovative DV methodologies (formal, simulation and emulation based) to continuously push the quality and efficiency of test benches
Develop and maintain emulation environment to collect metrics related to emulation environment
Will need to be in San Diego full time, 5 days a week
Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information.
Required Qualifications
5+ years of work experience with RTL/FPGA design (Verilog), embedded system architecture
5+ years of Design Verification, Emulation and Debug experience with simulation and emulation and prototyping flows
Preferred Qualifications
Knowledge of communication protocols such as AXI4-x, DDRx, PCIe, etc.
Strong System Verilog/UVM based verification skills & experience with assertion & coverage-based verification methodology
Good understanding of chip-level functional model building
Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C
Knowledge of Behavioral and Structural models and familiarity with simulation environments
Experience customizing and debugging make-based build flows and working with Xilinx’s Vivado tools
Experience with cm tools such as Git and Gerrit.
Experience in formal / static verification methodologies will be a plus
Experience with emulation platforms – Palladium, Zebu, Veloce, FPGAs.
Experience with synthesizing and optimizing designs and verification components developed in synthesizable Verilog.
Experience with C/C++ DPI transactors and monitors.
Develop environment to run verification test cases, OS boot, performance benchmarks and other vectors.
Design, develop, and maintain CAD infrastructure for silicon design teams enabling bring up, test and debug automations.
Execute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures.
Experience with debugging tools such as JTAG and lab test equipment such as logic analyzers, oscilloscopes, signal generators, etc.
Experience with GLS, and scripting languages such as Perl, Python is a plus
Linux OS proficiency
Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.
Salary $115,600.00 - $173,400.00
Benefits We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants. Highly competitive benefits package is designed to support your success at work, at home, and at play.
EEO Statement Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
Security Clearance Must be a U.S. citizen and eligible to receive a U.S. Government security clearance.
Location San Diego, CA
Remote Work Remote options available.
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Qualcomm Technologies, Inc.
Job Area
Engineering Group > ASICS Engineering
Role General Summary
Familiarity with RTL design in Verilog and System Verilog
Develop verification methodology, ensuring scalable and portable environment across simulation and emulation.
Develop test plan to verify Hardware building blocks, Design macros and Standard interfaces (PCIE, DDR, USB, I2C, SPI, etc)
Own end to end DV tasks from coding Test bench and test cases, write assertions, running simulations and achieving all coverage goals
Explore innovative DV methodologies (formal, simulation and emulation based) to continuously push the quality and efficiency of test benches
Develop and maintain emulation environment to collect metrics related to emulation environment
Will need to be in San Diego full time, 5 days a week
Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information.
Required Qualifications
5+ years of work experience with RTL/FPGA design (Verilog), embedded system architecture
5+ years of Design Verification, Emulation and Debug experience with simulation and emulation and prototyping flows
Preferred Qualifications
Knowledge of communication protocols such as AXI4-x, DDRx, PCIe, etc.
Strong System Verilog/UVM based verification skills & experience with assertion & coverage-based verification methodology
Good understanding of chip-level functional model building
Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C
Knowledge of Behavioral and Structural models and familiarity with simulation environments
Experience customizing and debugging make-based build flows and working with Xilinx’s Vivado tools
Experience with cm tools such as Git and Gerrit.
Experience in formal / static verification methodologies will be a plus
Experience with emulation platforms – Palladium, Zebu, Veloce, FPGAs.
Experience with synthesizing and optimizing designs and verification components developed in synthesizable Verilog.
Experience with C/C++ DPI transactors and monitors.
Develop environment to run verification test cases, OS boot, performance benchmarks and other vectors.
Design, develop, and maintain CAD infrastructure for silicon design teams enabling bring up, test and debug automations.
Execute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures.
Experience with debugging tools such as JTAG and lab test equipment such as logic analyzers, oscilloscopes, signal generators, etc.
Experience with GLS, and scripting languages such as Perl, Python is a plus
Linux OS proficiency
Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.
Salary $115,600.00 - $173,400.00
Benefits We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants. Highly competitive benefits package is designed to support your success at work, at home, and at play.
EEO Statement Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
Security Clearance Must be a U.S. citizen and eligible to receive a U.S. Government security clearance.
Location San Diego, CA
Remote Work Remote options available.
#J-18808-Ljbffr