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TPI Global Solutions

Power Management Engineer

TPI Global Solutions, Austin, Texas, us, 78716

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Power Management Engineer

Note: W2 Only Entry Level Role, No C2C Duration: Up to 2 years Entry level electrical engineer with strong communication skills and good electrical engineering fundamentals related to power dynamics Understanding of BIOS, OS, and driver interactions Soldering experience is a plus Experience building a PC or something EE-related is a plus Job Description: Seeking an enthusiastic electrical engineer to join our Power and Performance Customer Attainment team and work on best-in-class products. This is a design/test engineering position that entails working with multifunctional groups as well as clients/OEMs to innovate the technology implemented. The team is mainly focused on power validation of silicon products and debugging PC systems with an emphasis on platform-level debug. Education Requirements: Recent college graduate holding a degree in EE or equivalent (Bachelors) with no more than 3-5 years' experience - a candidate with a Masters will only be considered if it is recent and unrelated to their Bachelors Job Requirements: Should demonstrate strong EE fundamentals (analog/digital design, signal/power integrity, etc.) Strong understanding of BIOS, OS, and driver interactions at the system level as well as proficient understanding of x86 CPU architecture and functionality Experience in scripting and automation languages (Perl, PowerShell, Python, etc.) as well as a good familiarity with basic lab equipment, data acquisition devices, and switching power supplies is a plus Experience with leading PCB technology and electrical design and characterization of the following areas: DDR4/5, USB-C, LPDP, MIPI and I2C/SPI/UART buses is a plus Experience in one or more of: MCU, power (DC-DC converters, power management, low power design), analog circuits, display technology, and integration is a plus Experience in board CAD tools including Cadence Concept & Allegro is a plus The role is self-starting and the candidate should be able to deal with a high level of ambiguity as well as constant communication with the client/OEM, internal system and software engineers, external vendors, and System on Chip (SoC) architects to debug and improve power models and drivers used for future client programs.

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