Blue Origin
SLD FPGA Verification Engineer III - Lunar Permanence
Blue Origin, Merritt Island, Florida, us, 32954
Blue Origin is seeking a talented individual to join our team as a Validation Engineer. We envision millions of people living and working in space for the benefit of Earth, and we’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion.
This role is part of the Lunar Permanence business unit, which develops Blue Origin’s Blue Moon landers and related products. The successful candidate will participate in verification of FPGA-based solutions within Sustaining Lunar Development program’s avionics, guidance, and navigation group.
Key Responsibilities
Perform requirements-based verification of FPGAs using Universal Verification Methodology (UVM). Create comprehensive verification and validation plan that encompasses functional and system level verification and validation. Develop IP/subsystem/system level testbench and tests to achieve required coverage goals. Document plans and procedures. Write directed and random test cases. Generate reports in support of certification of the design to a high DAL. Qualifications
BS/MS in Electrical Engineering, Computer Engineering or a closely related field of study 5+ years experience verifying FPGAs or ASICSs In-depth experience using RTL simulation tools such as Siemens QuestaSim, ModelSim, or equivalent In-depth knowledge of System Verilog and the Universal Verification Methodology (UVM). Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc.) from scratch. Understands different types of coverage, usage of cover classes, cover points, etc. Experience with predictive testbench components, functional coverage and assertions. Experience with constrained random verification. Experience with the Register Abstraction Layer. Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program Reviewing verification and validation results against the coverage goals. Writing, analyzing and achieving coverage metrics. Experience of debugging skills to narrow down and isolate issue between RTL design and testbench or test case is required. Desired
Familiarity with the following are also helpful AXI protocols, PCIe, Ethernet, SPI, I2C interfaces Debugging FPGA/ASIC hardware and assisting with HW/SW integration. Managing regression and continuous integration infrastructure within GITLab Knowledge of scripting languages such as Python, Perl, or TCL/Shell for automation. Working knowledge of NPR 7150.2, DO-254, or other safety-critical software standard. Blue Origin offers a competitive compensation package, including a salary range of $126,898.00-$177,656.85 for WA applicants. Benefits include medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match of up to 5%, and an Education Support Program. Equal Employment Opportunity
Blue Origin is proud to be an Equal Opportunity/Affirmative Action Employer and is committed to attracting, retaining, and developing a highly qualified and dedicated work force. Blue Origin hires and promotes people on the basis of their qualifications, performance, and abilities.
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Perform requirements-based verification of FPGAs using Universal Verification Methodology (UVM). Create comprehensive verification and validation plan that encompasses functional and system level verification and validation. Develop IP/subsystem/system level testbench and tests to achieve required coverage goals. Document plans and procedures. Write directed and random test cases. Generate reports in support of certification of the design to a high DAL. Qualifications
BS/MS in Electrical Engineering, Computer Engineering or a closely related field of study 5+ years experience verifying FPGAs or ASICSs In-depth experience using RTL simulation tools such as Siemens QuestaSim, ModelSim, or equivalent In-depth knowledge of System Verilog and the Universal Verification Methodology (UVM). Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc.) from scratch. Understands different types of coverage, usage of cover classes, cover points, etc. Experience with predictive testbench components, functional coverage and assertions. Experience with constrained random verification. Experience with the Register Abstraction Layer. Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program Reviewing verification and validation results against the coverage goals. Writing, analyzing and achieving coverage metrics. Experience of debugging skills to narrow down and isolate issue between RTL design and testbench or test case is required. Desired
Familiarity with the following are also helpful AXI protocols, PCIe, Ethernet, SPI, I2C interfaces Debugging FPGA/ASIC hardware and assisting with HW/SW integration. Managing regression and continuous integration infrastructure within GITLab Knowledge of scripting languages such as Python, Perl, or TCL/Shell for automation. Working knowledge of NPR 7150.2, DO-254, or other safety-critical software standard. Blue Origin offers a competitive compensation package, including a salary range of $126,898.00-$177,656.85 for WA applicants. Benefits include medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match of up to 5%, and an Education Support Program. Equal Employment Opportunity
Blue Origin is proud to be an Equal Opportunity/Affirmative Action Employer and is committed to attracting, retaining, and developing a highly qualified and dedicated work force. Blue Origin hires and promotes people on the basis of their qualifications, performance, and abilities.
#J-18808-Ljbffr