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Mulya Technologies

Senior Analog/Mixed-Signal IC Design Engineer

Mulya Technologies, Fort Collins, Colorado, us, 80523

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Senior Analog/Mixed-Signal IC Design Engineer We are at the forefront of Wideband Signal Processing™ delivering high-performance, low-power analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and other mixed-signal IP cores. These components are crucial for a wide array of modern applications, including artificial intelligence (AI) infrastructure and advanced wireless communications such as 5G networks and optical communications, automotive networking, LiDAR, radar systems, SatComm, and Software Defined Radio.

Responsibilities

Senior Analog/Mixed-Signal Design Engineer

focusing on high-performance analog-to-digital and digital-to-analog converters. The successful candidate will perform high-performance transistor-level design from initial specification, through design and layout supervision, silicon evaluation and characterization to final product introduction to market.

Qualifications

5+ years of experience in high-performance analog or mixed-signal IC development in advanced CMOS processes

Thorough familiarity with high-speed, high-resolution analog-to-digital (ADC) or digital-to-analog (DAC) data converter design techniques. Experience in designing high performance building block circuits such as bandgap reference, op-amp, comparators, oscillators, DLL, PLL etc.

Must have a track record of successfully taking designs to production

Must have experience with evaluating silicon on bench and familiarity with standard lab equipment

Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis

Experience with analog and digital behavioral modeling, and/or synthesis of digital control blocks

Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools

MATLAB understanding would be preferred but not mandatory

Familiar with designing circuits for electromigration and ESD compliance in submicron CMOS process

Must be familiar with layout parasitic extraction tools and layout dependent impairments in advanced CMOS processes

Must be able to work independently, create and adhere to schedules

Must possess strong written and verbal communication skills with an ability to work with teams spread across geographic locations

Should be able to seek help proactively as well as share and pass on knowledge

Contact Contact:

Mining The Knowledge Community

Seniority level

Mid-Senior level

Employment type

Full-time

Job function

Design, Research, and Engineering

Industries

Semiconductor Manufacturing

Computer Hardware Manufacturing

Software Development

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