OSI Engineering
Base pay range
$170,000.00/yr - $196,000.00/yr
Overview A leading chip and silicon IP provider is seeking a talented Principal Verification Engineer to join its Memory Interconnect Design team. In this full-time hybrid role, you’ll work alongside world-class engineers to develop advanced technologies that make data faster and more secure.
Responsibilities
Technical leader for full-chip and block-level verification
Define verification plans in coordination with Architects, Logic, and Mixed-Signal Designers
Implement testbenches, monitors, and scoreboards using UVM methodology
Achieve functional and code coverage goals to ensure quality and completeness
Support silicon bring-up, lab testing, and debug in partnership with the System team
Contribute to the development of verification flows, tools, and methodology
Mentor and guide junior engineers within the team
Qualifications
Proficient in System Verilog or Verilog with significant UVM methodology experience
Significant Experience with standard ASIC Verification flow/software tools
Simulation tools: Synopsys VCS, Cadence Xcelium
Coverage & Analysis: Cadence IMC (Incisive Metrics Center)
Experience with scripting in Linux/Unix environments
Verification of DDR memory interfaces is desirable
Experience working in Analog/Mixed-Signal Products is desirable
Verification Methodologies: SVA (System/Verilog Assertions) is desirable
Regression Management: Jenkins (CI/CD Integration) is desirable
Demonstrated ability to lead and drive complex technical solutions
A strong commitment & ability to work in cross functional and globally dispersed teams
MS in Electrical Engineering and 10+ years, or PhD in EE and 7+ years of verification experience
Location San Jose, CA, Agoura Hilla, CA, Morrisville, NC and/or Johns Creek, GA (Hybrid)
Type Full-time
Salary Range $170,000–$196,000 (DOE)
No 3rd party agencies or C2C #J-18808-Ljbffr
Overview A leading chip and silicon IP provider is seeking a talented Principal Verification Engineer to join its Memory Interconnect Design team. In this full-time hybrid role, you’ll work alongside world-class engineers to develop advanced technologies that make data faster and more secure.
Responsibilities
Technical leader for full-chip and block-level verification
Define verification plans in coordination with Architects, Logic, and Mixed-Signal Designers
Implement testbenches, monitors, and scoreboards using UVM methodology
Achieve functional and code coverage goals to ensure quality and completeness
Support silicon bring-up, lab testing, and debug in partnership with the System team
Contribute to the development of verification flows, tools, and methodology
Mentor and guide junior engineers within the team
Qualifications
Proficient in System Verilog or Verilog with significant UVM methodology experience
Significant Experience with standard ASIC Verification flow/software tools
Simulation tools: Synopsys VCS, Cadence Xcelium
Coverage & Analysis: Cadence IMC (Incisive Metrics Center)
Experience with scripting in Linux/Unix environments
Verification of DDR memory interfaces is desirable
Experience working in Analog/Mixed-Signal Products is desirable
Verification Methodologies: SVA (System/Verilog Assertions) is desirable
Regression Management: Jenkins (CI/CD Integration) is desirable
Demonstrated ability to lead and drive complex technical solutions
A strong commitment & ability to work in cross functional and globally dispersed teams
MS in Electrical Engineering and 10+ years, or PhD in EE and 7+ years of verification experience
Location San Jose, CA, Agoura Hilla, CA, Morrisville, NC and/or Johns Creek, GA (Hybrid)
Type Full-time
Salary Range $170,000–$196,000 (DOE)
No 3rd party agencies or C2C #J-18808-Ljbffr