Hewlett Packard Enterprise
Principal ASIC Verification Engineer
Hewlett Packard Enterprise, San Jose, California, United States, 95199
Principal ASIC Verification Engineer
at
Hewlett Packard Enterprise
Location:
Sunnyvale, CA - Full time, Office 2 days per week.
Job Description Juniper Networks, part of Hewlett Packard Enterprise (HPE) is seeking a highly skilled and experienced Principal ASIC Verification Engineer to join our team. In this role, you will play a key part in verifying cutting‑edge ASIC/SoC designs for networking solutions. You will collaborate with a world‑class engineering team and contribute to the development of industry‑leading products.
Primary Responsibilities
Own and drive block‑level/subsystem/FullChip verification efforts, from creating test plans to achieving comprehensive coverage closure.
Develop, enhance, and maintain advanced UVM verification environments, including agents, sequences, scoreboards, virtual sequences, and register models.
Perform constraint‑driven random testing, debug complex SoC designs, and ensure functional coverage and assertion goals are met.
Analyze simulation results using industry‑leading simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and debug waveforms to validate design functionality.
Collaborate cross‑functional teams to identify and resolve issues, ensuring high‑quality ASIC/SoC deliverables.
Required Skills and Qualifications
12+ years of experience in ASIC/SoC verification with a proven track record of owning verification from test plan to coverage closure.
Strong expertise in SystemVerilog and UVM methodology, including developing environments from scratch.
Deep understanding of randomization, constraints, functional coverage, and assertions (SVA).
Hands‑on experience in test planning, coverage analysis, and debugging of complex SoC designs.
Proficiency with industry‑standard simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and waveform debugging.
Plus
Experience verifying networking ASICs or router datapath/control blocks, such as packet processing, forwarding engines, or fabric interfaces.
Familiarity with high‑speed interconnects, buffers, or scheduling pipelines in large networking SoCs.
Exposure to emulation environments, hardware acceleration, or traffic‑model integration.
Knowledge of coverage analytics, regression dashboards, and continuous‑integration flows (e.g., Jenkins).
Understanding of low‑power (UPF) or formal verification methodologies.
Experience with post‑silicon bring‑up and debug.
Familiarity with emulation environments and debug flows.
Equal Employment Opportunity Hewlett Packard Enterprise is an Equal Employment Opportunity / Veterans / Disabled / LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need.
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at
Hewlett Packard Enterprise
Location:
Sunnyvale, CA - Full time, Office 2 days per week.
Job Description Juniper Networks, part of Hewlett Packard Enterprise (HPE) is seeking a highly skilled and experienced Principal ASIC Verification Engineer to join our team. In this role, you will play a key part in verifying cutting‑edge ASIC/SoC designs for networking solutions. You will collaborate with a world‑class engineering team and contribute to the development of industry‑leading products.
Primary Responsibilities
Own and drive block‑level/subsystem/FullChip verification efforts, from creating test plans to achieving comprehensive coverage closure.
Develop, enhance, and maintain advanced UVM verification environments, including agents, sequences, scoreboards, virtual sequences, and register models.
Perform constraint‑driven random testing, debug complex SoC designs, and ensure functional coverage and assertion goals are met.
Analyze simulation results using industry‑leading simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and debug waveforms to validate design functionality.
Collaborate cross‑functional teams to identify and resolve issues, ensuring high‑quality ASIC/SoC deliverables.
Required Skills and Qualifications
12+ years of experience in ASIC/SoC verification with a proven track record of owning verification from test plan to coverage closure.
Strong expertise in SystemVerilog and UVM methodology, including developing environments from scratch.
Deep understanding of randomization, constraints, functional coverage, and assertions (SVA).
Hands‑on experience in test planning, coverage analysis, and debugging of complex SoC designs.
Proficiency with industry‑standard simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and waveform debugging.
Plus
Experience verifying networking ASICs or router datapath/control blocks, such as packet processing, forwarding engines, or fabric interfaces.
Familiarity with high‑speed interconnects, buffers, or scheduling pipelines in large networking SoCs.
Exposure to emulation environments, hardware acceleration, or traffic‑model integration.
Knowledge of coverage analytics, regression dashboards, and continuous‑integration flows (e.g., Jenkins).
Understanding of low‑power (UPF) or formal verification methodologies.
Experience with post‑silicon bring‑up and debug.
Familiarity with emulation environments and debug flows.
Equal Employment Opportunity Hewlett Packard Enterprise is an Equal Employment Opportunity / Veterans / Disabled / LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need.
#J-18808-Ljbffr