Mindlance
Description
As a Silicon Design Verification Engineer, you complete end-to-end tasks that are integrated into an overarching project, with minimal assistance from more senior team members. You make larger, mostly independent technical contributions by planning, managing, and executing your own priorities, selecting appropriate method(s) to most effectively achieve verification goals and objectives. You typically verify a piece of a major functional block within an IP. You demonstrate deep understanding of Design Verification and possess proficient knowledge of the hardware engineering process to deliver verified designs.
Responsibilities
Apply verification techniques and methodologies to verify designs, with minimal guidance (mostly independently).
Apply verification tools and languages (e.g., SystemVerilog) to verify designs, with minimal guidance (mostly independently).
Develop test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation can be easily understood and used, with minimal guidance (mostly independently).
Work closely with architecture and designers to help verify the functional correctness of the logic design with minimal guidance (mostly independently).
Collaborate with cross-functional teams to debug failures (e.g., boards, software, manufacturing, design, thermal issues).
Minimum Role Qualification
SV Coding Skills
Simulation-based Verification Techniques, Methodology, and Experience
Scripting and infrastructure
Domain specific knowledge
Testbench components and techniques
UVM Coding Skills
SVA Coding Skills
Formal Verification Techniques, Methodology, and Experience
Communication and comprehension
Problem-solving
EEO “Mindlance is an Equal Opportunity Employer and does not discriminate in employment on the basis of – Minority/Gender/Disability/Religion/LGBTQI/Age/Veterans.”
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Responsibilities
Apply verification techniques and methodologies to verify designs, with minimal guidance (mostly independently).
Apply verification tools and languages (e.g., SystemVerilog) to verify designs, with minimal guidance (mostly independently).
Develop test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation can be easily understood and used, with minimal guidance (mostly independently).
Work closely with architecture and designers to help verify the functional correctness of the logic design with minimal guidance (mostly independently).
Collaborate with cross-functional teams to debug failures (e.g., boards, software, manufacturing, design, thermal issues).
Minimum Role Qualification
SV Coding Skills
Simulation-based Verification Techniques, Methodology, and Experience
Scripting and infrastructure
Domain specific knowledge
Testbench components and techniques
UVM Coding Skills
SVA Coding Skills
Formal Verification Techniques, Methodology, and Experience
Communication and comprehension
Problem-solving
EEO “Mindlance is an Equal Opportunity Employer and does not discriminate in employment on the basis of – Minority/Gender/Disability/Religion/LGBTQI/Age/Veterans.”
#J-18808-Ljbffr