Correct Designs
Senior Design Verification Engineer (remote position)
Correct Designs, Austin, Texas, us, 78716
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Senior Design Verification Engineer (remote position)
role at
Correct Designs .
Correct Designs is seeking talented Verification Engineers with SystemVerilog UVM experience to work with major clients nationwide, including projects in AI, Machine Learning, SOC/ASIC products, aerospace FPGAs, medical electronics, RISC-V, ARM peripherals, and DSPs. These roles support verification of advanced CPU/GPU SOCs.
We offer long-term contracts, typically lasting around 3 years, with the possibility of shorter or longer terms. Our engineers enjoy respected positions, competitive hourly rates, health care, and retirement benefits. Contracts can be paused between projects, providing flexibility, or continued seamlessly for stability.
Based in Austin, TX, with clients across the US, opportunities include both in-person and remote work.
Responsibilities
Verify complex design blocks using SV/UVM environments
Develop and execute pre-silicon verification plans
Create directed and random verification tests
Develop verification components and tools
Implement verification functional coverage and analyze coverage results
Debug regression failures
Replicate and review functional issues for bug fixes
Required Skills and Experience
8+ years of verification experience in hardware development
Proficiency in SystemVerilog and UVM methodologies
Strong debugging skills with tools like DVE/Verdi
Object-Oriented programming, computer architecture, and data structures knowledge
Analytical, problem-solving skills with attention to detail
Excellent interpersonal and communication skills
Comfortable working across geographies
Desired Skills
Experience in verification environment architecture and scripting (Perl, Ruby, Make)
Knowledge of formal verification, RTL design, or software development
Education Bachelor's or Master's in Electrical Engineering, Computer Engineering, or Computer Science
Additional Details
Seniority Level: Mid-Senior
Employment Type: Full-time
Industry: Semiconductors
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Senior Design Verification Engineer (remote position)
role at
Correct Designs .
Correct Designs is seeking talented Verification Engineers with SystemVerilog UVM experience to work with major clients nationwide, including projects in AI, Machine Learning, SOC/ASIC products, aerospace FPGAs, medical electronics, RISC-V, ARM peripherals, and DSPs. These roles support verification of advanced CPU/GPU SOCs.
We offer long-term contracts, typically lasting around 3 years, with the possibility of shorter or longer terms. Our engineers enjoy respected positions, competitive hourly rates, health care, and retirement benefits. Contracts can be paused between projects, providing flexibility, or continued seamlessly for stability.
Based in Austin, TX, with clients across the US, opportunities include both in-person and remote work.
Responsibilities
Verify complex design blocks using SV/UVM environments
Develop and execute pre-silicon verification plans
Create directed and random verification tests
Develop verification components and tools
Implement verification functional coverage and analyze coverage results
Debug regression failures
Replicate and review functional issues for bug fixes
Required Skills and Experience
8+ years of verification experience in hardware development
Proficiency in SystemVerilog and UVM methodologies
Strong debugging skills with tools like DVE/Verdi
Object-Oriented programming, computer architecture, and data structures knowledge
Analytical, problem-solving skills with attention to detail
Excellent interpersonal and communication skills
Comfortable working across geographies
Desired Skills
Experience in verification environment architecture and scripting (Perl, Ruby, Make)
Knowledge of formal verification, RTL design, or software development
Education Bachelor's or Master's in Electrical Engineering, Computer Engineering, or Computer Science
Additional Details
Seniority Level: Mid-Senior
Employment Type: Full-time
Industry: Semiconductors
#J-18808-Ljbffr