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Correct Designs

Senior Design Verification Engineer (remote position)

Correct Designs, Austin, Texas, us, 78716

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Senior Design Verification Engineer (remote position)

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Senior Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position along with long-term stability and benefits? Correct Designs can give it all to you.

Correct Designs is currently seeking talented Verification Engineers with prior SystemVerilog UVM experience to work with our major clients in Austin, TX, and nationwide. Opportunities include projects in AI and Machine Learning, processor fabric subsystems, SOC/ASIC products for vision processing, aerospace FPGAs, medical electronics, RISC-V based SoC, ARM peripherals, and mixed signal DSPs. Successful candidates will support verification of advanced CPU/GPU based SOCs.

Correct Designs is not a typical contracting firm. Our engineers enjoy long-term roles with competitive hourly rates in excellent team environments. Contracts typically last around 3 years, with options for shorter or longer durations. We are respected in the Design Verification community, with clients seeking CDI engineers regularly. If you need breaks between contracts, you can take them without losing your place in line for new projects. We also provide healthcare and retirement benefits.

Our base is in Austin, Texas, with clients across the US. Both in-person and remote work are available.

Currently, our positions are filled, but we are continuously looking for skilled CDI engineers. Please submit your resume to be matched with upcoming projects.

Whether you're an experienced veteran or a talented engineer looking to broaden your experience, we offer exciting career options.

Responsibilities

Verify complex design blocks using SV/UVM verification environments.

Develop and execute pre-silicon verification test plans.

Create directed and random verification tests to validate functionality.

Develop verification components and tools.

Use industry-standard coverage analysis tools/methods to develop verification functional coverage.

Debug regression failures.

Replicate functional issues found externally or post-silicon; review/enhance tests to verify bug fixes.

Required Skills and Experience

8+ years of verification experience in hardware development.

Strong background in SystemVerilog and UVM methodologies.

Proficiency with debug tools such as DVE/Verdi.

Object-oriented programming, computer architecture, and data structures knowledge.

Excellent analytical, problem-solving, and attention to detail skills.

Strong interpersonal and communication skills.

Comfortable working across geographies.

Desired Skills

Experience in verification environment architecture, scripting (Perl, Ruby, Make).

Experience in formal verification, RTL design, or software development.

Education Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or Computer Science.

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