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The University of Texas at Austin

Product Engineer I - II or Sr. Product Engineer, Texas Institute for Electronics

The University of Texas at Austin, Campus, Illinois, us, 60920

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Product Engineer I - II or Sr. Product Engineer Location: PICKLE RESEARCH CAMPUS, Texas Institute for Electronics (TIE) – part of the Cockrell School of Engineering, University of Texas at Austin.

About Us TIE is a public‑private partnership of semiconductor, defense, and research institutions dedicated to advancing semiconductor packaging, 3D integration, and chip cooling.

Our mission is to help restore U.S. leadership in semiconductor manufacturing by developing cutting‑edge equipment and processes in advanced packaging, logic, memory, and heterogeneous integration.

Benefits

Competitive health benefits (employee premiums covered 100%, family premiums 50%)

Vision, dental, life, and disability insurance options

Generous paid vacation, sick time, and holidays

Teacher Retirement System of Texas – defined benefit retirement plan with 7.75% employer match

Additional voluntary retirement programs (403(b) and 457(b))

Flexible spending account options for medical and childcare expenses

LinkedIn Learning and conference opportunities

Tuition assistance

Expansive employee discount program (athletic tickets, libraries, museums, travel)

General Notes Multiple vacancies are available. Positions may be filled at a higher level based on experience. Applicants must be authorized to work in the U.S. without sponsorship. Relocation assistance may be available.

We are reviving advanced 3D/high‐density integrated (3DHI) packaging in the U.S. and seek motivated individuals to join our team.

Purpose Validate and optimize IC and test‐structure products, improving 3DHI yield, performance, and reliability across a wide range of customer materials and micro‑systems.

Responsibilities

Validate product and test vehicles against specifications; develop and optimize manufacturing/test workflows.

Contribute to the design and development of 2.5D/3D packaging solutions; support TIE’s 3D‑ADK.

Interpret fab metrology, defect data, and yield; correlate silicon and simulation to assess process variations.

Drive corrective actions across cross‑functional teams; perform failure analysis on TIE products.

Collaborate with design teams to ensure package compatibility with die and system requirements; design and execute DOE studies.

Stay current with industry trends and emerging technologies in semiconductor packaging.

Define product DFT & DFM requirements; assist with ATE test‑plan definitions.

Validate and characterize IC solutions in bench/lab to assess multi‑physics impacts.

Leverage data analytics to optimize product yield and reliability.

Own the product life cycle from bring‑up to qualification.

Collaborate with customers on field failures.

Required Qualifications

Product Engineer I: Bachelor’s degree in Electrical Engineering, Semiconductor Physics, Computer Science, Materials Science, or related field.

Product Engineer II: Bachelor’s degree in the same fields and a minimum of three years of industry experience.

Senior Product Engineer: Bachelor’s degree and a minimum of ten years of industry experience.

Strong understanding of semiconductor device physics and mixed‑signal IC behavior.

Proficient programming skills in Python, MATLAB, C/C++, or Perl for data analysis and automation.

Excellent communication and teamwork skills; ability to collaborate with cross‑functional teams.

Excellent analytical and problem‑solving skills with attention to detail.

Ability to thrive in a fast‑paced environment and manage multiple projects.

(Eng II or Senior): Prior experience in semiconductor design, product engineering, process integration/manufacturing, test, or packaging.

Relevant education and/or industry experience may be substituted as appropriate.

Preferred Qualifications

Master’s or PhD in semiconductor engineering, Electrical Engineering, Materials Science, Semiconductor Physics, or related discipline.

Experience or interest in one or more: IC/micro‑system design, product validation, test, process or wafer‑fab integration, semiconductor packaging manufacturing, thermal/stress optimization, quality assurance, ATE, bench validation, failure analysis, materials packaging/stress/strain evaluation, data analytics (JMP, Power BI, Excel), BIST definition and validation.

Experience in a startup or R&D environment.

Salary Range TIE pays industry competitive salaries.

Working Conditions

On‑site work in a scientific research environment with dynamic prototyping facilities.

Work outside standard office hours may be required occasionally during peak periods and special events.

Required Materials

Resume/CV

Three work references with contact information; at least one supervisor reference

Letter of interest

Equal Opportunity Employer The University of Texas at Austin is an equal opportunity/affirmative action employer and complies with all applicable federal and state laws regarding nondiscrimination and affirmative action. The University is committed to a policy of equal opportunity for all persons and does not discriminate on the basis of race, color, national origin, age, marital status, sex, sexual orientation, gender identity, gender expression, disability, religion, or veteran status in employment, educational programs, and activities, and admissions.

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