Google
Join to apply for the
Senior SoC Power Architect, Silicon
role at
Google 4 days ago Be among the first 25 applicants Join to apply for the
Senior SoC Power Architect, Silicon
role at
Google Get AI-powered advice on this job and more exclusive features. Note: By applying to this position you will have an opportunity to share your preferred working location from the following:
Mountain View, CA, USA; San Diego, CA, USA . Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 5 years of experience with computer architecture concepts, including microarchitecture, cache hierarchy, pipelining, and memory subsystems. 5 years of experience in SoC power management or low power design/methodology. Experience with Application-Specific Integrated Circuit (ASIC) low power flows and power management concepts.
Preferred qualifications:
Master's Degree or PhD in Electronics or Computer Engineering/Science, with an emphasis on computer architecture, performance and power analysis. 8 years of experience in SoC power management or low power design/methodology. Experience in CPU power in mobile SoCs from CPU architecture and design to schedulers, governors and post-silicon tuning for power and performance. Experience with ASIC power modeling/estimation, defining power goals, power roll-ups, power/voltage domains design and low power architectures/optimization techniques. Experience with software and architectural design decisions on system power and thermal behavior. Experience with ASIC design flows from concept to post-silicon.
About The Job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .
Responsibilities
Define and drive low power solutions for Google System on a Chips (SoC) to optimize Power-Performance-Area (PPA) under peak current and thermal constraints with a focus on the CPU subsystem. Define power key performance indicators and SoC/IP-level power goals, guide architecture, design and implementation to achieve power goals, create power models, perform power roll ups and track power throughout the design cycle. Propose and drive power optimizations, both hardware and software, throughout the design process from concept to mass productization. Drive power-performance trade-off analysis for engineering reviews and product road-map decisions. Perform post-silicon characterization and productization of power features.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form . Seniority level
Seniority level Mid-Senior level Employment type
Employment type Full-time Job function
Job function Other, Information Technology, and Engineering Industries Information Services and Technology, Information and Internet Referrals increase your chances of interviewing at Google by 2x Sign in to set job alerts for “Security Operations Center Architect” roles.
Cloud & Network Security Engineer (Palo Alto & AWS/Azure Specialist)
San Diego, CA $71,976.00-$104,844.00 22 hours ago Information Technology Infrastructure Engineer
Staff Security Engineer (Detection Engineering)
Sr. Infrastructure Engineer – AWS Certified, Intune (Hybrid; Contract-to-Hire)
Functional Safety Engineer, Senior Staff
We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
#J-18808-Ljbffr
Senior SoC Power Architect, Silicon
role at
Google 4 days ago Be among the first 25 applicants Join to apply for the
Senior SoC Power Architect, Silicon
role at
Google Get AI-powered advice on this job and more exclusive features. Note: By applying to this position you will have an opportunity to share your preferred working location from the following:
Mountain View, CA, USA; San Diego, CA, USA . Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 5 years of experience with computer architecture concepts, including microarchitecture, cache hierarchy, pipelining, and memory subsystems. 5 years of experience in SoC power management or low power design/methodology. Experience with Application-Specific Integrated Circuit (ASIC) low power flows and power management concepts.
Preferred qualifications:
Master's Degree or PhD in Electronics or Computer Engineering/Science, with an emphasis on computer architecture, performance and power analysis. 8 years of experience in SoC power management or low power design/methodology. Experience in CPU power in mobile SoCs from CPU architecture and design to schedulers, governors and post-silicon tuning for power and performance. Experience with ASIC power modeling/estimation, defining power goals, power roll-ups, power/voltage domains design and low power architectures/optimization techniques. Experience with software and architectural design decisions on system power and thermal behavior. Experience with ASIC design flows from concept to post-silicon.
About The Job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .
Responsibilities
Define and drive low power solutions for Google System on a Chips (SoC) to optimize Power-Performance-Area (PPA) under peak current and thermal constraints with a focus on the CPU subsystem. Define power key performance indicators and SoC/IP-level power goals, guide architecture, design and implementation to achieve power goals, create power models, perform power roll ups and track power throughout the design cycle. Propose and drive power optimizations, both hardware and software, throughout the design process from concept to mass productization. Drive power-performance trade-off analysis for engineering reviews and product road-map decisions. Perform post-silicon characterization and productization of power features.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form . Seniority level
Seniority level Mid-Senior level Employment type
Employment type Full-time Job function
Job function Other, Information Technology, and Engineering Industries Information Services and Technology, Information and Internet Referrals increase your chances of interviewing at Google by 2x Sign in to set job alerts for “Security Operations Center Architect” roles.
Cloud & Network Security Engineer (Palo Alto & AWS/Azure Specialist)
San Diego, CA $71,976.00-$104,844.00 22 hours ago Information Technology Infrastructure Engineer
Staff Security Engineer (Detection Engineering)
Sr. Infrastructure Engineer – AWS Certified, Intune (Hybrid; Contract-to-Hire)
Functional Safety Engineer, Senior Staff
We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
#J-18808-Ljbffr