OCTOPYD
One of our partner companies are seeking a
Senior VLSI Design Engineer
to contribute to the design, verification, and optimization of cutting-edge hardware solutions for AI acceleration and next-generation semiconductor architectures. This role is ideal for someone passionate about bridging hardware and AI/ML, with experience in RTL design, synthesis, verification, and performance optimization. You will collaborate closely with AI researchers, software engineers, and systems architects to translate advanced AI algorithms into efficient, production-ready hardware designs. Responsibilities RTL Design & Verification:
Develop, simulate, and verify RTL code for high-performance, low-power digital designs. PPA Optimization:
Optimize designs for Power, Performance, and Area, using industry-standard synthesis and place-and-route flows. Architecture Collaboration:
Work with system architects to define microarchitectures for AI accelerators, memory subsystems, and interconnects. Hardware-Software Co-Design:
Collaborate with software and AI teams to co-optimize hardware architectures for ML workloads. EDA Tools & Flows:
Use tools such as Synopsys, Cadence, or Mentor for synthesis, timing analysis, and formal verification. Design Reviews:
Conduct peer reviews, ensure design quality, and maintain documentation for reproducibility. Prototype & Lab Bring-up:
Support FPGA prototyping and lab validation of designs. Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 5+ years of experience in digital ASIC or FPGA design, including RTL coding (Verilog/SystemVerilog/VHDL). Strong knowledge of VLSI design flows, synthesis, timing closure, and verification methodologies (UVM, SystemVerilog). Experience with PPA optimization and low-power design techniques. Familiarity with AI/ML algorithms and their hardware implications is a plus. Strong problem-solving and debugging skills, with attention to detail. Excellent collaboration and communication skills. Nice-to-Haves Experience in high-bandwidth memory interfaces, interconnect protocols, or custom accelerators. Knowledge of hardware security, reliability, or fault tolerance for mission-critical systems. Familiarity with LLMs, neural network inference optimizations, or AI-specific hardware accelerators. Experience in mixed-signal or photonics-based VLSI design. Why Join Us Work at the forefront of AI and semiconductor innovation. Collaborate with a multidisciplinary team spanning AI, software, and hardware. Competitive compensation, benefits, and opportunities for career growth. Be part of a mission-driven team creating transformative technology. Seniority level
Seniority level Mid-Senior level Employment type
Employment type Full-time Job function
Industries Semiconductor Manufacturing and Software Development Referrals increase your chances of interviewing at OCTOPYD by 2x Inferred from the description for this job
Medical insurance Vision insurance 401(k) Get notified when a new job is posted. Sign in to set job alerts for “Design Engineer” roles.
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Senior VLSI Design Engineer
to contribute to the design, verification, and optimization of cutting-edge hardware solutions for AI acceleration and next-generation semiconductor architectures. This role is ideal for someone passionate about bridging hardware and AI/ML, with experience in RTL design, synthesis, verification, and performance optimization. You will collaborate closely with AI researchers, software engineers, and systems architects to translate advanced AI algorithms into efficient, production-ready hardware designs. Responsibilities RTL Design & Verification:
Develop, simulate, and verify RTL code for high-performance, low-power digital designs. PPA Optimization:
Optimize designs for Power, Performance, and Area, using industry-standard synthesis and place-and-route flows. Architecture Collaboration:
Work with system architects to define microarchitectures for AI accelerators, memory subsystems, and interconnects. Hardware-Software Co-Design:
Collaborate with software and AI teams to co-optimize hardware architectures for ML workloads. EDA Tools & Flows:
Use tools such as Synopsys, Cadence, or Mentor for synthesis, timing analysis, and formal verification. Design Reviews:
Conduct peer reviews, ensure design quality, and maintain documentation for reproducibility. Prototype & Lab Bring-up:
Support FPGA prototyping and lab validation of designs. Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 5+ years of experience in digital ASIC or FPGA design, including RTL coding (Verilog/SystemVerilog/VHDL). Strong knowledge of VLSI design flows, synthesis, timing closure, and verification methodologies (UVM, SystemVerilog). Experience with PPA optimization and low-power design techniques. Familiarity with AI/ML algorithms and their hardware implications is a plus. Strong problem-solving and debugging skills, with attention to detail. Excellent collaboration and communication skills. Nice-to-Haves Experience in high-bandwidth memory interfaces, interconnect protocols, or custom accelerators. Knowledge of hardware security, reliability, or fault tolerance for mission-critical systems. Familiarity with LLMs, neural network inference optimizations, or AI-specific hardware accelerators. Experience in mixed-signal or photonics-based VLSI design. Why Join Us Work at the forefront of AI and semiconductor innovation. Collaborate with a multidisciplinary team spanning AI, software, and hardware. Competitive compensation, benefits, and opportunities for career growth. Be part of a mission-driven team creating transformative technology. Seniority level
Seniority level Mid-Senior level Employment type
Employment type Full-time Job function
Industries Semiconductor Manufacturing and Software Development Referrals increase your chances of interviewing at OCTOPYD by 2x Inferred from the description for this job
Medical insurance Vision insurance 401(k) Get notified when a new job is posted. Sign in to set job alerts for “Design Engineer” roles.
Mechanical Engineer (Autonomous Vehicles)
Mechanical Design Engineer – Mechanical Integration
Menlo Park, CA $108,000.00-$123,000.00 2 weeks ago Staff / Principal Mechanical Engineer, Instruments and Composites
Mechanical Engineer, Data Center Engineering
Mechanical Engineer - Thermal / Fluids Hardware Design
Menlo Park, CA $108,000.00-$123,000.00 2 weeks ago Redwood City, CA $125,000.00-$140,000.00 1 month ago South San Francisco, CA $95,000.00-$115,000.00 4 months ago Senior Mechanical Design Engineer - Mechanical Integration
Menlo Park, CA $126,000.00-$148,000.00 2 weeks ago Redwood City, CA $76,000.00-$98,000.00 2 weeks ago Redwood City, CA $120,000.00-$200,000.00 3 weeks ago Senior Mechanical Engineer, Instruments and Composites
South San Francisco, CA $115,000.00-$150,000.00 4 weeks ago San Mateo, CA $116,450.00-$137,000.00 1 week ago San Carlos, CA $95,000.00-$145,000.00 1 month ago Senior Mechanical Design Engineer - Vehicle Interiors
South San Francisco, CA $130,000.00-$150,000.00 2 months ago Foster City, CA $180,000.00-$290,000.00 4 months ago Senior Mechanical Engineer - Thermal / Fluids Hardware Design
Menlo Park, CA $126,000.00-$148,000.00 2 weeks ago South San Francisco, CA $120,000.00-$145,000.00 4 months ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
#J-18808-Ljbffr