TetraMem - Accelerate The World
Analog/Mixed-Signal Verification Engineer
TetraMem - Accelerate The World, San Jose, California, United States, 95199
Analog/Mixed-Signal Verification Engineer
Analog/Mixed-Signal Verification Engineer
6 days ago Be among the first 25 applicants Develop and implement mixed-signal verification and coverage plans for complex IC designs based on design architecture and specifications Design and develop verification testbenches using industry-standard verification languages and methodologies Write and execute test cases to verify mixed-signal circuits for functionality, performance, and reliability Review and analyze verification results, and provide feedback to design teams Collaborate with design and layout teams to identify and resolve design issues Develop new verification methodologies, tools, and techniques, ensuring scalability and portability Sign-off mixed signal designs in preparation for tapeout Write behavioral models from custom analog and mixed-signal circuits in SystemVerilog HDL Collaborate with circuit design teams to understand fine details of custom circuits Collaborate with Design Verification team to craft hooks into the behavioral models for effective verification Run various simulations and equivalence checks to ensure that the model matches closely with the custom circuits Write scripts and simple tools for automating repetitive tasks Optimize and refine models to ensure accuracy while maintaining efficient simulation performance Review and analyze verification results, and provide feedback to design team Document modeling techniques and results for internal and external dissemination Keep updated with industry trends in modeling techniques
Responsibilities
Develop and implement mixed-signal verification and coverage plans for complex IC designs based on design architecture and specifications Design and develop verification testbenches using industry-standard verification languages and methodologies Write and execute test cases to verify mixed-signal circuits for functionality, performance, and reliability Review and analyze verification results, and provide feedback to design teams Collaborate with design and layout teams to identify and resolve design issues Develop new verification methodologies, tools, and techniques, ensuring scalability and portability Sign-off mixed signal designs in preparation for tapeout Write behavioral models from custom analog and mixed-signal circuits in SystemVerilog HDL Collaborate with circuit design teams to understand fine details of custom circuits Collaborate with Design Verification team to craft hooks into the behavioral models for effective verification Run various simulations and equivalence checks to ensure that the model matches closely with the custom circuits Write scripts and simple tools for automating repetitive tasks Optimize and refine models to ensure accuracy while maintaining efficient simulation performance Review and analyze verification results, and provide feedback to design team Document modeling techniques and results for internal and external dissemination Keep updated with industry trends in modeling techniques
Requirements
Bachelor's degree in Electrical Engineering and 5+ years of relevant industry experience or equivalent Strong understanding of analog and mixed-signal circuit design and verification principles Ability to write test plans, present results, and communicate clearly with multi-functional teams Have a familiarity with verification methodologies and tools: simulators, waveform viewers, execution automation, simulation time optimization, and coverage collection Familiarity with analog behavioral models is a plus Deep knowledge of Verilog/SystemVerilog with ability to write synthesize-able and behavioral code Deep knowledge of digital logic gates, clocking and state elements Deep knowledge of SPICE simulation, HDL simulation and logic equivalence tools Working understanding of analog circuit architecture such as ADC, DAC, LDO, Charge pump, etc. Have good programming skills and can write efficient programs or scripts in Perl, Python, and/or C Excellent debugging, problem-solving and analytical skills Strong communication and teamwork skills
Salary Range:
$110,000 - $300,000 / year Seniority level
Seniority level Mid-Senior level Employment type
Employment type Full-time Job function
Job function Strategy/Planning and Information Technology Industries Computer Hardware Manufacturing Referrals increase your chances of interviewing at TetraMem - Accelerate The World by 2x Inferred from the description for this job
Medical insurance Vision insurance 401(k) Get notified about new Validation Engineer jobs in
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Analog/Mixed-Signal Verification Engineer
6 days ago Be among the first 25 applicants Develop and implement mixed-signal verification and coverage plans for complex IC designs based on design architecture and specifications Design and develop verification testbenches using industry-standard verification languages and methodologies Write and execute test cases to verify mixed-signal circuits for functionality, performance, and reliability Review and analyze verification results, and provide feedback to design teams Collaborate with design and layout teams to identify and resolve design issues Develop new verification methodologies, tools, and techniques, ensuring scalability and portability Sign-off mixed signal designs in preparation for tapeout Write behavioral models from custom analog and mixed-signal circuits in SystemVerilog HDL Collaborate with circuit design teams to understand fine details of custom circuits Collaborate with Design Verification team to craft hooks into the behavioral models for effective verification Run various simulations and equivalence checks to ensure that the model matches closely with the custom circuits Write scripts and simple tools for automating repetitive tasks Optimize and refine models to ensure accuracy while maintaining efficient simulation performance Review and analyze verification results, and provide feedback to design team Document modeling techniques and results for internal and external dissemination Keep updated with industry trends in modeling techniques
Responsibilities
Develop and implement mixed-signal verification and coverage plans for complex IC designs based on design architecture and specifications Design and develop verification testbenches using industry-standard verification languages and methodologies Write and execute test cases to verify mixed-signal circuits for functionality, performance, and reliability Review and analyze verification results, and provide feedback to design teams Collaborate with design and layout teams to identify and resolve design issues Develop new verification methodologies, tools, and techniques, ensuring scalability and portability Sign-off mixed signal designs in preparation for tapeout Write behavioral models from custom analog and mixed-signal circuits in SystemVerilog HDL Collaborate with circuit design teams to understand fine details of custom circuits Collaborate with Design Verification team to craft hooks into the behavioral models for effective verification Run various simulations and equivalence checks to ensure that the model matches closely with the custom circuits Write scripts and simple tools for automating repetitive tasks Optimize and refine models to ensure accuracy while maintaining efficient simulation performance Review and analyze verification results, and provide feedback to design team Document modeling techniques and results for internal and external dissemination Keep updated with industry trends in modeling techniques
Requirements
Bachelor's degree in Electrical Engineering and 5+ years of relevant industry experience or equivalent Strong understanding of analog and mixed-signal circuit design and verification principles Ability to write test plans, present results, and communicate clearly with multi-functional teams Have a familiarity with verification methodologies and tools: simulators, waveform viewers, execution automation, simulation time optimization, and coverage collection Familiarity with analog behavioral models is a plus Deep knowledge of Verilog/SystemVerilog with ability to write synthesize-able and behavioral code Deep knowledge of digital logic gates, clocking and state elements Deep knowledge of SPICE simulation, HDL simulation and logic equivalence tools Working understanding of analog circuit architecture such as ADC, DAC, LDO, Charge pump, etc. Have good programming skills and can write efficient programs or scripts in Perl, Python, and/or C Excellent debugging, problem-solving and analytical skills Strong communication and teamwork skills
Salary Range:
$110,000 - $300,000 / year Seniority level
Seniority level Mid-Senior level Employment type
Employment type Full-time Job function
Job function Strategy/Planning and Information Technology Industries Computer Hardware Manufacturing Referrals increase your chances of interviewing at TetraMem - Accelerate The World by 2x Inferred from the description for this job
Medical insurance Vision insurance 401(k) Get notified about new Validation Engineer jobs in
San Jose, CA . Menlo Park, CA $144,000.00-$201,000.00 2 weeks ago Sr. Test and Validation Engineer, Drive Unit Test and Validation
San Jose, CA $90,000.00-$120,000.00 2 months ago Mountain View, CA $196,000.00-$248,000.00 5 days ago San Jose, CA $100,000.00-$130,000.00 20 hours ago San Jose, CA $159,800.00-$202,300.00 6 days ago San Jose, CA $141,280.00-$211,920.00 1 week ago Fremont, CA $90,000.00-$100,000.00 1 month ago Santa Clara, CA $108,000.00-$224,250.00 1 day ago Verification and Validation Engineer/Senior V&V Engineer
Mountain View, CA $120,000.00-$134,000.00 1 week ago Verification and Validation Engineer/Senior V&V Engineer
San Mateo County, CA $120,000.00-$150,000.00 1 week ago Verification and Validation Engineer/Senior V&V Engineer
Fremont, CA $120,000.00-$150,000.00 1 week ago Fremont, CA $75,000.00-$95,000.00 4 days ago Test and Validation Engineer II, Drive Unit Test and Validation
Fremont, CA $90,000.00-$100,000.00 1 month ago Palo Alto, CA $196,000.00-$208,000.00 2 weeks ago San Jose, CA $130,000.00-$154,000.00 4 days ago Mountain View, CA $140,000.00-$220,000.00 8 hours ago Vehicle Verification and Validation Engineer
San Jose, CA $120,000.00-$150,000.00 1 week ago Systems Validation Engineer, Efficiency & EV Systems
Milpitas, CA $120,000.00-$170,000.00 4 days ago Supplier Quality Engineer, Body in White
San Jose, CA $142,000.00-$221,605.00 23 hours ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
#J-18808-Ljbffr