Apple Inc.
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a results-oriented and hardworking Timing Design Engineer. As a member of our team, you will have the opportunity to craft products that delight millions of Apple customers daily. In this role, you will collaborate with architecture, CAD, and logic design teams, impacting PHY design and timing closure efforts.
Description
As an ASIC STA Engineer, your responsibilities include timing sign-off, flow development, and ownership of IP and block-level timing constraints, from synthesis to sign-off. You will work closely with RTL designers, CAD teams, and Physical design teams to understand design intent, develop timing constraints, and facilitate timing closure. Innovation in timing constraints and flow is encouraged to ensure successful timing closure. Minimum Qualifications
BS degree in a technical discipline with at least 3 years of relevant experience. Preferred Qualifications
Thorough knowledge of ASIC timing closure flow and methodology. At least 2+ years of experience in ASIC timing constraints and closure, expertise in STA tools (Primetime), scripting (Tcl, Perl), and familiarity with synthesis, DFT, and backend methodologies. Strong communication skills and a self-motivated attitude. Note: The compensation range for this role is between $139,500 and $258,100, depending on experience and location. Apple offers comprehensive benefits, including stock programs, medical coverage, retirement plans, educational reimbursement, and more. Apple is an equal opportunity employer committed to diversity and inclusion. #J-18808-Ljbffr
As an ASIC STA Engineer, your responsibilities include timing sign-off, flow development, and ownership of IP and block-level timing constraints, from synthesis to sign-off. You will work closely with RTL designers, CAD teams, and Physical design teams to understand design intent, develop timing constraints, and facilitate timing closure. Innovation in timing constraints and flow is encouraged to ensure successful timing closure. Minimum Qualifications
BS degree in a technical discipline with at least 3 years of relevant experience. Preferred Qualifications
Thorough knowledge of ASIC timing closure flow and methodology. At least 2+ years of experience in ASIC timing constraints and closure, expertise in STA tools (Primetime), scripting (Tcl, Perl), and familiarity with synthesis, DFT, and backend methodologies. Strong communication skills and a self-motivated attitude. Note: The compensation range for this role is between $139,500 and $258,100, depending on experience and location. Apple offers comprehensive benefits, including stock programs, medical coverage, retirement plans, educational reimbursement, and more. Apple is an equal opportunity employer committed to diversity and inclusion. #J-18808-Ljbffr