Apple Inc.
Would you like to join Apple’s growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development, emphasizing highly energy-efficient design and innovative technologies that enhance user experience. Our world-class, vertically integrated engineering team spans RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering.
Role: SOC Verification Engineer You will be responsible for pre-silicon RTL verification of blocks and top-level SOC. With a deep understanding of SOC architecture and meticulous attention to detail, you will collaborate across disciplines to develop reusable testbenches and verification environments using the latest methodologies and metric-driven verification.
Responsibilities include:
Understanding various architecture types, including industry-standard low power architectures, and building block/chip level testbenches using best-in-class verification methodologies.
Creating detailed verification plans based on specifications in collaboration with architects.
Developing reusable block/IP level testbenches and supporting IP integration verification.
Generating directed and constrained-random tests.
Creating and analyzing coverage models to improve test coverage.
Building automated flows for block and chip level verification.
Debugging failures, managing bug tracking, and closing coverage gaps.
Conducting detailed verification reviews and setting standards for coding quality.
Collaborating with team members to improve methodologies and workflows.
Minimum Qualifications:
BS degree with 10+ years of relevant experience.
Expertise in HVL and HDL (SystemVerilog, Verilog).
Advanced knowledge of HVL methodologies (UVM/OVM/VMM).
Strong verification skills including problem solving, constrained random testing, and debugging.
Understanding of reusable verification frameworks.
Knowledge of digital logic design, chip architecture, and microarchitecture.
Excellent communication skills and a collaborative mindset.
Preferred Qualifications:
Knowledge of industry-standard interfaces.
Experience with SystemVerilog Assertion (SVA).
Experience with IP verification and integration verification.
Familiarity with IP development and release flows.
Programming skills in C, Python, Perl, C++, and assembly.
Experience with embedded CPU verification.
Ability to define coverage spaces and develop coverage models.
Experience with low power verification and wireless protocols like Bluetooth and WiFi.
Knowledge of formal verification tools (e.g., JasperGold).
Apple offers a competitive total compensation package, including base salary, stock programs, comprehensive benefits, and educational reimbursements. The salary range for this role is $171,600 to $302,200, depending on skills and experience.
Apple is an equal opportunity employer committed to diversity and inclusion. We encourage applicants of all backgrounds to apply.
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Role: SOC Verification Engineer You will be responsible for pre-silicon RTL verification of blocks and top-level SOC. With a deep understanding of SOC architecture and meticulous attention to detail, you will collaborate across disciplines to develop reusable testbenches and verification environments using the latest methodologies and metric-driven verification.
Responsibilities include:
Understanding various architecture types, including industry-standard low power architectures, and building block/chip level testbenches using best-in-class verification methodologies.
Creating detailed verification plans based on specifications in collaboration with architects.
Developing reusable block/IP level testbenches and supporting IP integration verification.
Generating directed and constrained-random tests.
Creating and analyzing coverage models to improve test coverage.
Building automated flows for block and chip level verification.
Debugging failures, managing bug tracking, and closing coverage gaps.
Conducting detailed verification reviews and setting standards for coding quality.
Collaborating with team members to improve methodologies and workflows.
Minimum Qualifications:
BS degree with 10+ years of relevant experience.
Expertise in HVL and HDL (SystemVerilog, Verilog).
Advanced knowledge of HVL methodologies (UVM/OVM/VMM).
Strong verification skills including problem solving, constrained random testing, and debugging.
Understanding of reusable verification frameworks.
Knowledge of digital logic design, chip architecture, and microarchitecture.
Excellent communication skills and a collaborative mindset.
Preferred Qualifications:
Knowledge of industry-standard interfaces.
Experience with SystemVerilog Assertion (SVA).
Experience with IP verification and integration verification.
Familiarity with IP development and release flows.
Programming skills in C, Python, Perl, C++, and assembly.
Experience with embedded CPU verification.
Ability to define coverage spaces and develop coverage models.
Experience with low power verification and wireless protocols like Bluetooth and WiFi.
Knowledge of formal verification tools (e.g., JasperGold).
Apple offers a competitive total compensation package, including base salary, stock programs, comprehensive benefits, and educational reimbursements. The salary range for this role is $171,600 to $302,200, depending on skills and experience.
Apple is an equal opportunity employer committed to diversity and inclusion. We encourage applicants of all backgrounds to apply.
#J-18808-Ljbffr