Cadence
Principal FPGA Design Engineer - FPGA IPs (R48199/rj)
Cadence, San Jose, California, United States, 95199
This range is provided by Cadence. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.
Base pay range
$170,000.00/yr - $190,000.00/yr Job Summary
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Protium Prototyping Platform is part of the Cadence Dynamic Duo that has been a huge success with our customers. This role involves designing, verifying, performing timing closure, and hardware validation of the FPGA IPs. Key Responsibilities
Developing field-programmable gate array intellectual properties (FPGA IPs) for Protium platform, including design, verification, integration, timing closure, documentation and releasing the IPs to end users; Working on FPGA IP Design, Verification/Simulation, Timing closure, Validation of IP on the hardware; Enhancing current IPs as well as developing new IPs; Debugging and fixing internal regression failures for FPGA IPs; Documenting IPs. Minimum Qualifications
The ideal candidate will have the following skills and experience: Master's degree in Electrical Engineering with 5+ years of experience; Experience with FPGA design and verification using Verilog; Experience with high-end Xilinx(AMD) FPGAs including using Vivado tool for simulation, place and route; Experience in debugging FPGAs in the lab using Vivado hardware manager, debugging with firmware/software; Experience using Cadence Simulators Incisive or Xcelium; Detailed knowledge about industry standard interfaces such as PCI Express, DRAM/DDR4, SRAM, I2C, JTAG, AXI. Seniority Level
Mid-Senior level Employment Type
Full-time Job Function
Engineering and Information Technology Industries
Computer Hardware Manufacturing Benefits
Medical insurance Vision insurance 401(k) Paid maternity leave Paid paternity leave Tuition assistance
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$170,000.00/yr - $190,000.00/yr Job Summary
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Protium Prototyping Platform is part of the Cadence Dynamic Duo that has been a huge success with our customers. This role involves designing, verifying, performing timing closure, and hardware validation of the FPGA IPs. Key Responsibilities
Developing field-programmable gate array intellectual properties (FPGA IPs) for Protium platform, including design, verification, integration, timing closure, documentation and releasing the IPs to end users; Working on FPGA IP Design, Verification/Simulation, Timing closure, Validation of IP on the hardware; Enhancing current IPs as well as developing new IPs; Debugging and fixing internal regression failures for FPGA IPs; Documenting IPs. Minimum Qualifications
The ideal candidate will have the following skills and experience: Master's degree in Electrical Engineering with 5+ years of experience; Experience with FPGA design and verification using Verilog; Experience with high-end Xilinx(AMD) FPGAs including using Vivado tool for simulation, place and route; Experience in debugging FPGAs in the lab using Vivado hardware manager, debugging with firmware/software; Experience using Cadence Simulators Incisive or Xcelium; Detailed knowledge about industry standard interfaces such as PCI Express, DRAM/DDR4, SRAM, I2C, JTAG, AXI. Seniority Level
Mid-Senior level Employment Type
Full-time Job Function
Engineering and Information Technology Industries
Computer Hardware Manufacturing Benefits
Medical insurance Vision insurance 401(k) Paid maternity leave Paid paternity leave Tuition assistance
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