Apple Inc.
Cupertino, California, United States
Description
As a member of the Emulation verification team, you will play a key role in using Emulation for verification of large SoCs. Your responsibilities will include porting the design onto the Palladium platform, completing detailed Emulation test plans, and collaborating closely with Architecture, Design, DV, Silicon Validation, Power, and Software teams to bring up large SoCs on the emulation platform. You will develop and apply synthesizable monitors and checkers, prepare and review test plans with multi-functional teams, perform low power testing on the emulation platform, and develop code for design and verification using Verilog, SystemVerilog, and UVM. Additionally, you will develop random stimulus infrastructure by reusing existing UVM simulation constraints. Minimum Qualifications
BS degree with 10+ years of relevant industry experience. Preferred Qualifications
Understanding of the tool flow from RTL to Emulation is a plus. Experience with Standard Emulator (Palladium, Veloce, Zebu) or FPGA (Xilinx, Altera) flow. Proficiency in writing synthesizable SystemVerilog/Verilog code and assertions. Experience with SystemVerilog verification environments including C/C++ DPI and UVM. Experience in writing and debugging test firmware. Scripting experience (Perl, Python, TCL). Excellent analytical and debugging skills. Experience with UVM Acceleration is a plus. This role offers a base pay range between $181,100 and $318,400, depending on skills, qualifications, experience, and location. Apple provides comprehensive benefits, including medical and dental coverage, retirement plans, stock programs, educational reimbursement, and more. Additional bonuses, commissions, or relocation benefits may be available. Apple is an equal opportunity employer committed to inclusion and diversity. We promote equal opportunity regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other protected characteristics.
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As a member of the Emulation verification team, you will play a key role in using Emulation for verification of large SoCs. Your responsibilities will include porting the design onto the Palladium platform, completing detailed Emulation test plans, and collaborating closely with Architecture, Design, DV, Silicon Validation, Power, and Software teams to bring up large SoCs on the emulation platform. You will develop and apply synthesizable monitors and checkers, prepare and review test plans with multi-functional teams, perform low power testing on the emulation platform, and develop code for design and verification using Verilog, SystemVerilog, and UVM. Additionally, you will develop random stimulus infrastructure by reusing existing UVM simulation constraints. Minimum Qualifications
BS degree with 10+ years of relevant industry experience. Preferred Qualifications
Understanding of the tool flow from RTL to Emulation is a plus. Experience with Standard Emulator (Palladium, Veloce, Zebu) or FPGA (Xilinx, Altera) flow. Proficiency in writing synthesizable SystemVerilog/Verilog code and assertions. Experience with SystemVerilog verification environments including C/C++ DPI and UVM. Experience in writing and debugging test firmware. Scripting experience (Perl, Python, TCL). Excellent analytical and debugging skills. Experience with UVM Acceleration is a plus. This role offers a base pay range between $181,100 and $318,400, depending on skills, qualifications, experience, and location. Apple provides comprehensive benefits, including medical and dental coverage, retirement plans, stock programs, educational reimbursement, and more. Additional bonuses, commissions, or relocation benefits may be available. Apple is an equal opportunity employer committed to inclusion and diversity. We promote equal opportunity regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other protected characteristics.
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