Tech Providers,
Performance Modeling/Verification Engineer - Intermediate (US)
Tech Providers,, Santa Clara, California, us, 95053
Job Title:
Performance Modeling/Verification Engineer – Intermediate Location:
Santa Clara, CA Duration:
12+ months Description:
Develop, enhance, and maintain
SystemC/TLM2
models for memory controllers, peripherals, and interconnects, ensuring they accurately simulate the behavior and performance characteristics of the hardware. Collaborate with cross teams to integrate models intotools used for system-level designs, ensuring proper functionality and performance. Identify
bottlenecks and performance issues
within models and work to optimize their performance to meet design specifications. Develop and execute testbenches
to
validate
the functionality and correctness of models, as well as participate in system-level testing and debugging. Create clear and comprehensive documentation for models, including usage guidelines and design specifications. Deliverables:
Cycle approximate performance models SV/UVM Functional and Performance Verification Experience and Education:
5 or more years of proven modeling & verification experience on large ASIC development projects or software/firmware experience in a hardware development setting; Strong background in C/C++ development in a Linux Environment; Strong debug skills and experience with debug tools such as Gdb, Valgrind ; Knowledge of Perl and Makefiles; Experience in Verilog/SystemVerilog/SystemC, preferred; Experience in C/Verilog environment using DPI/PLI, preferred; PCIe & AXI Knowledge Preferred
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Performance Modeling/Verification Engineer – Intermediate Location:
Santa Clara, CA Duration:
12+ months Description:
Develop, enhance, and maintain
SystemC/TLM2
models for memory controllers, peripherals, and interconnects, ensuring they accurately simulate the behavior and performance characteristics of the hardware. Collaborate with cross teams to integrate models intotools used for system-level designs, ensuring proper functionality and performance. Identify
bottlenecks and performance issues
within models and work to optimize their performance to meet design specifications. Develop and execute testbenches
to
validate
the functionality and correctness of models, as well as participate in system-level testing and debugging. Create clear and comprehensive documentation for models, including usage guidelines and design specifications. Deliverables:
Cycle approximate performance models SV/UVM Functional and Performance Verification Experience and Education:
5 or more years of proven modeling & verification experience on large ASIC development projects or software/firmware experience in a hardware development setting; Strong background in C/C++ development in a Linux Environment; Strong debug skills and experience with debug tools such as Gdb, Valgrind ; Knowledge of Perl and Makefiles; Experience in Verilog/SystemVerilog/SystemC, preferred; Experience in C/Verilog environment using DPI/PLI, preferred; PCIe & AXI Knowledge Preferred
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