Apple Inc.
Wireless SOC Design Verification Engineer
Apple Inc., Sunnyvale, California, United States, 94087
Wireless SOC Design Verification Engineer
As part of our team, you will have the opportunity to verify complex SOCs. Our team integrates multiple sophisticated IP-level DV environments, crafts highly reusable UVM Testbenches, implements coverage-driven and directed test cases, deploys new tools, and enhances methodologies to improve tape-out readiness. Collaborating across Apple, you can push industry boundaries of wireless systems and improve the product experience globally. You will learn about large-scale SOC architectures, high-speed layered protocols, low-power methodologies, wireless protocols, FW-HW interactions, and multi-chip SOC debug architecture. Description
As a Design Verification Engineer, you'll be central to verification within our silicon design group, responsible for pre-silicon RTL verification of blocks and top-level SOCs. You should be comfortable with all areas of SoC Design Verification, thrive in a dynamic environment, debate ideas openly, and meet complex wireless protocol requirements. Key areas include High Efficiency SOC Architecture, peripherals like SPI, I2C, UART, Timer, DMA, memory management, low-power specs, multi-processor systems, DDR, PCIe, Memory Controllers, USB, PLL, power-up schemes, and Secured Boot. You will develop coverage-driven verification plans, architect UVM-based test benches, integrate VIPs, achieve coverage targets, and collaborate with design, architecture, SW, FW, and IP teams. You will also work with DV methodology architects to improve verification flows. Minimum Qualifications
BS degree + 3 years of industry experience. Preferred Qualifications
ASIC DV experience. Knowledge of HVL methodology (UVM/OVM), recent UVM experience. Formal verification experience. Full ASIC cycle experience from concept to tape-out and bring-up. Verification of large SOC systems with embedded processors. Hands-on verification of PCIe, Bus Fabric, NOC, AHB, AXI in UVM. Experience with low power design, UPF, boot-up, power-cycling, HW/FW interaction verification. Knowledge of Low Power Verification. At Apple, base pay ranges from $147,400 to $272,100, depending on skills, experience, and location. Employees can participate in stock programs, receive benefits like medical coverage, retirement plans, discounts, educational reimbursement, and may be eligible for bonuses or relocation assistance. Apple is an equal opportunity employer committed to diversity and inclusion. We promote equal opportunity regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other protected characteristics.
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As part of our team, you will have the opportunity to verify complex SOCs. Our team integrates multiple sophisticated IP-level DV environments, crafts highly reusable UVM Testbenches, implements coverage-driven and directed test cases, deploys new tools, and enhances methodologies to improve tape-out readiness. Collaborating across Apple, you can push industry boundaries of wireless systems and improve the product experience globally. You will learn about large-scale SOC architectures, high-speed layered protocols, low-power methodologies, wireless protocols, FW-HW interactions, and multi-chip SOC debug architecture. Description
As a Design Verification Engineer, you'll be central to verification within our silicon design group, responsible for pre-silicon RTL verification of blocks and top-level SOCs. You should be comfortable with all areas of SoC Design Verification, thrive in a dynamic environment, debate ideas openly, and meet complex wireless protocol requirements. Key areas include High Efficiency SOC Architecture, peripherals like SPI, I2C, UART, Timer, DMA, memory management, low-power specs, multi-processor systems, DDR, PCIe, Memory Controllers, USB, PLL, power-up schemes, and Secured Boot. You will develop coverage-driven verification plans, architect UVM-based test benches, integrate VIPs, achieve coverage targets, and collaborate with design, architecture, SW, FW, and IP teams. You will also work with DV methodology architects to improve verification flows. Minimum Qualifications
BS degree + 3 years of industry experience. Preferred Qualifications
ASIC DV experience. Knowledge of HVL methodology (UVM/OVM), recent UVM experience. Formal verification experience. Full ASIC cycle experience from concept to tape-out and bring-up. Verification of large SOC systems with embedded processors. Hands-on verification of PCIe, Bus Fabric, NOC, AHB, AXI in UVM. Experience with low power design, UPF, boot-up, power-cycling, HW/FW interaction verification. Knowledge of Low Power Verification. At Apple, base pay ranges from $147,400 to $272,100, depending on skills, experience, and location. Employees can participate in stock programs, receive benefits like medical coverage, retirement plans, discounts, educational reimbursement, and may be eligible for bonuses or relocation assistance. Apple is an equal opportunity employer committed to diversity and inclusion. We promote equal opportunity regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other protected characteristics.
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