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Finite Element Analysis (FEA) Engineering
ZipRecruiter, San Jose, California, United States, 95199
Job DescriptionJob Description
About Etched
Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video models and extremely deep & parallel chain-of-thought reasoning agents.
Finite Element Analysis (FEA) Engineering
Job Summary
Join our Advanced IC Packaging Team as a Finite Element Analysis (FEA) Engineering focused on Chip-on-Wafer-on-Substrate (CoWoS) package development. You'll use ANSYS Mechanical APDL to perform critical thermo-mechanical analysis and contribute to next- high-performance computing systems.
Key Responsibilities
Develop FEA models for CoWoS-based IC packages using ANSYS Mechanical APDL
Perform thermo-mechanical stress/strain analysis and thermal cycling simulations
Analyze package warpage, solder joint reliability, and interconnect stress
Optimize CoWoS package designs including silicon interposers
Collaborate with electrical engineering teams on package development
Technical Skills: Proficiency in ANSYS Mechanical APDL for structural and thermal FEA
Understanding of semiconductor packaging materials and processes
Strong grasp on non-linear properties of materials (elastic-plastic, viscoelastic)
Familiarity with CoWoS-S/L/R, TSVs, or 2.5D/3D integration concepts
Basic
programming/scripting
skills (APDL, Python, MATLAB)
CAD experience (SolidWorks or similar)
Bonus Points: Knowledge of solder joint reliability and failure analysis
Familiarity with JEDEC standards and reliability testing
Previous in semiconductor industry
Education & Experience: Pursuing a degree (Senior or Masters) in Mechanical Engineering or related field
1-2 years’ experience with IC packaging or semiconductor mechanical design
Academic or project experience with advanced packaging technologies
Program Details: 12-week paid
Generous housing support for those relocating
Based at our office in San Jose, CA
Direct mentorship from industry leaders and world-class engineers
Opportunity to work on one of the most important problems of our time
How we’re different Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs. We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
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Perform thermo-mechanical stress/strain analysis and thermal cycling simulations
Analyze package warpage, solder joint reliability, and interconnect stress
Optimize CoWoS package designs including silicon interposers
Collaborate with electrical engineering teams on package development
Technical Skills: Proficiency in ANSYS Mechanical APDL for structural and thermal FEA
Understanding of semiconductor packaging materials and processes
Strong grasp on non-linear properties of materials (elastic-plastic, viscoelastic)
Familiarity with CoWoS-S/L/R, TSVs, or 2.5D/3D integration concepts
Basic
programming/scripting
skills (APDL, Python, MATLAB)
CAD experience (SolidWorks or similar)
Bonus Points: Knowledge of solder joint reliability and failure analysis
Familiarity with JEDEC standards and reliability testing
Previous in semiconductor industry
Education & Experience: Pursuing a degree (Senior or Masters) in Mechanical Engineering or related field
1-2 years’ experience with IC packaging or semiconductor mechanical design
Academic or project experience with advanced packaging technologies
Program Details: 12-week paid
Generous housing support for those relocating
Based at our office in San Jose, CA
Direct mentorship from industry leaders and world-class engineers
Opportunity to work on one of the most important problems of our time
How we’re different Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs. We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
#J-18808-Ljbffr