AMD
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Senior RTL Design Engineer
role at
AMD Continue with Google Continue with Google Join to apply for the
Senior RTL Design Engineer
role at
AMD This range is provided by AMD. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more. Base pay range
$159,840.00/yr - $239,760.00/yr WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
The Role
We are looking for a self-motivated senior design engineer to be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. As a key contributor, you will focus on RTL design and validation of high-speed interfaces such as chip-to-chip interconnect, both on system and on package, and highly configurable mufti-protocol PHYs. Continuous technical innovation to increase productivity, to heighten quality of results, and to foster career development is integral to the role.
THE PERSON:
You have a passion for digital design. You are a team player. You have strong analytical and problem-solving skills. You are willing to learn and ready to take ownership of problems.
KEY RESPONSIBILITIES:
Perform RTL design of the digital components. Develop and validate timing constraints involving multiple clock domains while working with physical design to harden IP Help lead and mentor other engineers to achieve project goals and organizational growth. Work with a functional (design) verification team to meet coverage and quality standards. Analyze/fix Lint and CDC/RDC errors of the components. Guarantee quality/timely deliverables meeting project’s schedule. Help to improve and automate design process. Support post-silicon product bring-up/debug.
PREFERRED EXPERIENCE:
Strong experience in designing digital components for high performance, low power SOC/FPGA. Design of digital circuits and components using Verilog/System Verilog Creating and maintenance of timing constraints for complex multi-clock designs Debugging in digital and mixed-signal simulation environment. Power-optimization of digital designs. Multi-clock domain designs. Experience/Knowledge of High speed SerDes/Physical layer is a plus Logic synthesis, timing closure, logical equivalence checking and ECOs. Scripting languages such as Perl, Tcl, or Python. Collaboration with verification team. Excellent verbal and interpersonal communication skills. Excellent technical communications. Ability to produce technical documentation. Exhibit strong ownership of tasks and responsibilities.
ACADEMIC CREDENTIALS:
Bachelors or Masters degree in Electrical Engineering with relevant industry experience
LOCATION:
San Jose, California
Benefits offered are described:
AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Seniority level
Seniority level Mid-Senior level Employment type
Employment type Full-time Job function
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Senior RTL Design Engineer
role at
AMD Continue with Google Continue with Google Join to apply for the
Senior RTL Design Engineer
role at
AMD This range is provided by AMD. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more. Base pay range
$159,840.00/yr - $239,760.00/yr WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
The Role
We are looking for a self-motivated senior design engineer to be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. As a key contributor, you will focus on RTL design and validation of high-speed interfaces such as chip-to-chip interconnect, both on system and on package, and highly configurable mufti-protocol PHYs. Continuous technical innovation to increase productivity, to heighten quality of results, and to foster career development is integral to the role.
THE PERSON:
You have a passion for digital design. You are a team player. You have strong analytical and problem-solving skills. You are willing to learn and ready to take ownership of problems.
KEY RESPONSIBILITIES:
Perform RTL design of the digital components. Develop and validate timing constraints involving multiple clock domains while working with physical design to harden IP Help lead and mentor other engineers to achieve project goals and organizational growth. Work with a functional (design) verification team to meet coverage and quality standards. Analyze/fix Lint and CDC/RDC errors of the components. Guarantee quality/timely deliverables meeting project’s schedule. Help to improve and automate design process. Support post-silicon product bring-up/debug.
PREFERRED EXPERIENCE:
Strong experience in designing digital components for high performance, low power SOC/FPGA. Design of digital circuits and components using Verilog/System Verilog Creating and maintenance of timing constraints for complex multi-clock designs Debugging in digital and mixed-signal simulation environment. Power-optimization of digital designs. Multi-clock domain designs. Experience/Knowledge of High speed SerDes/Physical layer is a plus Logic synthesis, timing closure, logical equivalence checking and ECOs. Scripting languages such as Perl, Tcl, or Python. Collaboration with verification team. Excellent verbal and interpersonal communication skills. Excellent technical communications. Ability to produce technical documentation. Exhibit strong ownership of tasks and responsibilities.
ACADEMIC CREDENTIALS:
Bachelors or Masters degree in Electrical Engineering with relevant industry experience
LOCATION:
San Jose, California
Benefits offered are described:
AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Seniority level
Seniority level Mid-Senior level Employment type
Employment type Full-time Job function
Job function Engineering, Information Technology, and Design Industries Semiconductor Manufacturing Referrals increase your chances of interviewing at AMD by 2x Get notified about new Senior Design Engineer jobs in
San Jose, CA . Sunnyvale, CA $170,000 - $240,000 1 week ago Sunnyvale, CA $204,000 - $281,000 3 days ago Milpitas, CA $80,000.00 - $115,000.00 1 week ago Sr. Manager, Mechanical Design Engineering, Energy
Sr. Mechanical Design Engineer, Power Electronics
Sr. Mechanical Design Engineer, Test Infrastructure & Systems Engineering
Design Manager, Ecosystem and Collaboration UI
San Jose, CA $133,100.00 - $256,500.00 1 week ago Sr. Mechanical Design Engineer - Wafer Chucks & Wafer Positioning Stages
Sr. Mechanical Design Engineer - Wafer Chucks & Wafer Positioning Stages
Milpitas, CA $114,100.00 - $194,000.00 4 days ago Senior Design and Simulation Engineer (HIL)
San Francisco Bay Area $160,000.00 - $240,000.00 3 weeks ago Milpitas, CA $140,700.00 - $239,200.00 5 days ago Senior Mechanical Engineer - Low Voltage Electronics
San Francisco Bay Area $180,000.00 - $240,000.00 3 weeks ago Senior Mechanical Engineer (Vision Equipment)
Sunnyvale, CA $129,000.00 - $218,300.00 5 days ago CAD/CAM Engineering Manager 2 - R10197802
Sunnyvale, CA $142,200.00 - $213,400.00 1 week ago Palo Alto, CA $167,400.00 - $209,300.00 2 weeks ago Senior Mechanical Engineer – Interconnect Design
San Jose, CA $200,000.00 - $230,000.00 1 week ago Sr. Opto-Mechanical Design Engineer (Opto-Mech camera development technical lead)
San Francisco Bay Area $180,000.00 - $240,000.00 2 weeks ago Santa Clara, CA $247,000.00 - $260,000.00 18 hours ago Sr. Design for Reliability Manager - Mechanical Systems
Palo Alto, CA $237,200 - $296,500 2 weeks ago Mountain View, CA $178,000 - $265,000 2 weeks ago Senior Digital/Mixed-Signal IC Design Engineer
Software Engineering Manager - AI Hardware Systems Co-Design
Sunnyvale, CA $177,000 - $251,000 3 days ago Mountain View, CA $183,000 - $271,000 21 hours ago San Jose, CA $200,000 - $300,000 2 weeks ago Manager, Digital Design - Mixed-Signal High-Speed I/O SerDes
Software Engineering Manager - AI Systems Co-Design
We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
#J-18808-Ljbffr