Memory Subsystem Architecture and Performance Modeling

Memory Subsystem Architecture and Performance Modeling

Join to apply for the Memory Subsystem Architecture and Performance Modeling role at Rivos Inc.

Memory Subsystem Architecture and Performance Modeling

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Join to apply for the Memory Subsystem Architecture and Performance Modeling role at Rivos Inc.

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Join a cutting-edge and well-funded hardware startup in Silicon Valley as a SoC Performance Architect. Our mission is to reimagine silicon and create RISC-V based accelerated computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.
We are looking for experienced candidates.
Responsibilities

• Define architecture and microarchitecture for memory subsystem components including cache, interconnects and memory.
• Work with architecture and design teams to develop performance models in C++ for design space exploration and provide feedback to architecture and design teams.
• Validate the performance model against the specification and correlate with RTL.
• Plan and analyze results of performance studies analyzing micro-architectural proposals.
• Develop performance verification tests to ensure quality of model and design.
  
  

Requirements

• Strong knowledge in SoC architecture and power/performance trade-offs.
• Proficient at SW programming with good understanding of C/C++, Python, and modular object oriented software development.
• Experience in simulators for perf model development and perf analysis. Experience in different modeling techniques from analytical, event driven and cycle accurate.
• In-depth knowledge of memory subsystem architecture, microarchitecture and design including caches, cache coherency, NOC, LPDDR/DDR/HBM, and IO.
• Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
• Knowledge of SystemVerilog and waveform debugging tools is a plus.
• Ability to work collaboratively in a team and be productive under aggressive schedules.
  
  

Education And Experience

• Bachelor’s degree plus 5 years of industry experience.
• Master’s degree plus 3 years of industry experience.
• Ph.D with internship experience.

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Job function

  Design, Art/Creative, and Information Technology

• Industries

  Computer Hardware Manufacturing

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