Senior Field-Programmable Gate Arrays Engineer

Senior Field-Programmable Gate Arrays Engineer

Support FPGA debug, simulation, and test activities for existing platforms, focusing on defined features and escalations.

Create updated RTL designs for identified issues and block-level simulations using UVMF.

Support test case generation for UVMF and assist in mono, functional, and software integration through customer delivery.

Hard Skills:

• Writing and updating VHDL RTL
• Advanced FPGA design using VHDL and module/multi-module verification with SystemVerilog
• Proficient with automated self-checking test bench verification (QuestaSim) in UVM
• Ability to perform timing simulations, post-route simulations, and static timing analysis
• Experience with hardware development tools and IDEs for Xilinx devices (e.g., Vivado)
• Knowledge of FPGA concepts, architectures, and protocols (SOC, bus topology, CDC, PCIe, TSN, UART, SPI, AXI, PTP, SRIO, etc.)

Nice to have:

• Experience with Siemens UVMF
• Experience with Xilinx Zynq UltraScale+ MPSOC
• Additional experience with Altera development tools

Soft Skills:

• Ability to interpret data, information, and documents
• Creative problem-solving skills for complex issues
• Attention to detail and high-quality work
• Effective performance under demanding environments and changing workloads
• Clear and professional communication
• Ability to collaborate effectively with team members

Note: The job is still active and accepting applications.