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Location: Bay Area, CA
We are seeking a skilled Verification Engineer with expertise in low-power design verification and UVM/SystemVerilog. You will be responsible for developing and executing verification strategies for complex low-power IPs/blocks, ensuring power-aware functionality and high-quality silicon.
Key Responsibilities:
- Develop and implement power-aware verification strategies using UPF/CPF.
- Create and optimize UVM-based testbenches for block-level verification.
- Perform Gate-Level Simulations (GLS) to validate power intent and functional correctness.
- Debug and resolve issues related to power domains, retention, isolation, and level shifting.
- Achieve functional and code coverage closure using advanced verification techniques.
- Collaborate with RTL designers to identify and fix design bugs.
Required Skills & Experience:
- 5+ years of experience in ASIC/SoC verification.
- Strong expertise in SystemVerilog & UVM methodology.
- Hands-on experience with low-power verification (UPF/CPF).
- Proficiency in Gate-Level Simulation (GLS) and power-aware debugging.
- Familiarity with industry tools (VCS, NC-Verilog, Xcelium, Verdi).
- Ability to own block-level verification independently.
Seniority level
Seniority level
Mid-Senior level
Employment type
Employment type
Contract
Job function
Industries
Semiconductor Manufacturing, Computers and Electronics Manufacturing, and IT Services and IT Consulting
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