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Netlist

ASIC Engineer

Netlist, Irvine

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ASIC / SoC Design Engineer

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Reports To: VP, ASIC Engineering

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Company Overview:

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Netlist Inc. (NASDAQ: NLST) is a leading provider of high-performance modular memory subsystems and next-generation storage-class memory solutions. We specialize in cutting-edge technologies that enable innovation in AI, cloud computing, and enterprise infrastructure. Our product portfolio includes DDR4/DDR5 DIMMs, NAND-based SSDs, and advanced interconnect technologies such as CXL and PCIe .

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Join our world-class engineering team and be part of shaping the future of memory and storage architecture.

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Position Summary:

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Netlist is seeking an experienced and innovative ASIC / SoC Design Engineer to contribute to the development of advanced memory subsystem controllers and interface technologies. In this role, you will work from high-level architectural specifications to define microarchitectures, implement RTL, integrate third-party IPs, and deliver PPA-optimized ASIC/SoC designs through to tape-out.

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Key Responsibilities:

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  • Translate architectural specifications into block-level microarchitecture with a focus on power, performance, and area (PPA) optimization
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  • Develop synthesizable RTL in Verilog or SystemVerilog for custom controller, interface, and logic modules
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  • Integrate and validate third-party IP cores including PCIe , CXL , DDR3/4/5 , NAND , and SSD-related interfaces
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  • Perform functional simulations , unit-level verification , and assertion-based checks
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  • Execute logic synthesis , static timing analysis (STA) , clock domain crossing (CDC) checks, and timing closure
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  • Collaborate across hardware, firmware, validation, and physical design teams to drive full-chip integration
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  • Support bring-up and post-silicon validation of ASICs and FPGA prototypes
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  • Contribute to design reviews, documentation, and test planning
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Required Qualifications:

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  • BS in Electrical or Computer Engineering with 10+ years of relevant design experience, or
    nMS with 8+ years in ASIC / SoC hardware development

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  • Demonstrated expertise in PCIe , CXL , DDR3/DDR4/DDR5 , NAND flash , and SSD controller design

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  • Solid understanding of RTL design , digital logic principles, and ASIC/SoC development flows

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  • Proficient in EDA tools for synthesis, STA , and CDC analysis

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  • Experience integrating and validating commercial IP blocks in complex SoC environments

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  • Strong debugging , problem-solving, and analytical skills

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  • Excellent communication and documentation abilities

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Preferred Qualifications:

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  • Tape-out experience with high-performance ASICs or SoCs
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  • Familiarity with HLS tools , formal verification , or low-power design flows
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  • Experience with FPGA prototyping platforms (Xilinx, Intel/Altera)
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  • Background in memory controller or storage-class memory architecture
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  • Prior experience in CXL controller design or verification
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Why Join Netlist:

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  • Contribute to pioneering work in CXL , DDR5 , and next-gen memory technologies
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  • Work alongside some of the industry's top engineers in ASIC, memory systems, and storage
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  • Enjoy a collaborative and agile work culture focused on innovation
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  • Competitive compensation and comprehensive benefits package
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  • Flexible work environment including remote opportunities
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