Itlearn360
ASIC Physical Design Engineer at Acara Solutions Colorado Springs, CO
Itlearn360, Colorado Springs, Colorado, United States, 80509
ASIC Physical Design Engineer job at Acara Solutions. Colorado Springs, CO.
Acara Solutions is seeking a ASIC Physical Design Engineer to join our client on a
Fully Remote
opportunity Overview We're seeking an experienced ASIC/SoC Physical Design Engineer with strong synthesis expertise. This role covers the complete physical chip design flow-from RTL/gate-level netlist through tape-out-working on floorplanning, clock tree synthesis, routing, and timing closure. You will collaborate closely with design, verification, and customer teams to deliver high-performance silicon. Key Responsibilities Execute end-to-end ASIC/SoC physical design flow: RTL/gate netlist to tape-out. Perform floorplanning, die sizing, macro/IO placement, and congestion analysis. Run synthesis, constraints, and support multi-corner multi-mode (MCMM) optimization. Develop power/ground distribution networks and UPF methodologies. Perform clock tree synthesis (CTS), routing optimization, and static timing analysis (STA). Support ECOs, engineering debug, and physical verification (EM/IR analysis, DRC/LVS). Collaborate with internal and external teams; support technical presentations. Job Requirements Required Skills / Qualifications: 10+ years of ASIC/SoC physical design (8 yrs w/ MS / 5 yrs w/ PhD) Preferred Skills / Qualifications: Strong background in IC physical design, transistor layout, and design flows. Expertise with Synopsys tools (especially IC Compiler II). Experience with place & route, CTS, timing closure, EM/IR methodologies, and DFM. Proficiency with revision-control tools. Aleron companies (Acara Solutions, Aleron Shared Resources, Broadleaf Results, Lume Strategies, TalentRise, Viaduct) are an Equal Opportunity Employer. Race/Color/Gender/Religion/National Origin/Disability/Veteran. Applicants for this position must be legally authorized to work in the United States. This position does not meet the employment requirements for individuals with F-1 OPT STEM work authorization status.
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Acara Solutions is seeking a ASIC Physical Design Engineer to join our client on a
Fully Remote
opportunity Overview We're seeking an experienced ASIC/SoC Physical Design Engineer with strong synthesis expertise. This role covers the complete physical chip design flow-from RTL/gate-level netlist through tape-out-working on floorplanning, clock tree synthesis, routing, and timing closure. You will collaborate closely with design, verification, and customer teams to deliver high-performance silicon. Key Responsibilities Execute end-to-end ASIC/SoC physical design flow: RTL/gate netlist to tape-out. Perform floorplanning, die sizing, macro/IO placement, and congestion analysis. Run synthesis, constraints, and support multi-corner multi-mode (MCMM) optimization. Develop power/ground distribution networks and UPF methodologies. Perform clock tree synthesis (CTS), routing optimization, and static timing analysis (STA). Support ECOs, engineering debug, and physical verification (EM/IR analysis, DRC/LVS). Collaborate with internal and external teams; support technical presentations. Job Requirements Required Skills / Qualifications: 10+ years of ASIC/SoC physical design (8 yrs w/ MS / 5 yrs w/ PhD) Preferred Skills / Qualifications: Strong background in IC physical design, transistor layout, and design flows. Expertise with Synopsys tools (especially IC Compiler II). Experience with place & route, CTS, timing closure, EM/IR methodologies, and DFM. Proficiency with revision-control tools. Aleron companies (Acara Solutions, Aleron Shared Resources, Broadleaf Results, Lume Strategies, TalentRise, Viaduct) are an Equal Opportunity Employer. Race/Color/Gender/Religion/National Origin/Disability/Veteran. Applicants for this position must be legally authorized to work in the United States. This position does not meet the employment requirements for individuals with F-1 OPT STEM work authorization status.
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