Altera
Senior FPGA Compiler Software Engineer page is loaded Senior FPGA Compiler Software Engineer Apply locations San Jose, California, United States time type Full time posted on Posted 5 Days Ago job requisition id R01170
Job Details:
Job Description:
Become a member of our world-class software research and development team! Altera develops programmable logic technologies to accelerate innovation for many customers worldwide. You will be designing and developing leading-edge software innovations for Quartus, the tool that optimizes our FPGA devices, within a research-oriented team. The Quartus Placement optimization engines are key to unlocking high performance, area and power efficiency for our customer's design applications. As part of the Quartus Placement team, your role will include: Actively researching & developing novel optimization algorithms for our FPGA CAD software tools, including timing-driven analytic placement, detailed placement, partitioning and floorplanning
Developing and optimizing the software to drive performance improvements by leveraging innovative FPGA hardware features
Ideal candidates exhibit the following behavioral traits: Intellectual curiosity and a passion for exploring new technology
Excellent problem-solving, debugging, and attention to detail
Great communication, teamwork, and interpersonal skills
Salary Range The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. $178.9k - $259.0k USD #LI-CG1 Qualifications:
Minimum Requirements: Degree in Electrical Engineering, Computer Engineering, Computer Science or related field.
MS + 10 years of industry software experience, or PhD + 5 years of industry software experience
Desired/Preferred Skills: Significant experience coding & hands-on development of high performance multi-core software systems
Extensive experience developing EDA placement optimization algorithms
Proven leadership skills for collaborative cross functional projects
Experience with Altera Quartus or AMD Vivado software
Experience with combinatorial/continuous optimization, including but not limited to Boolean SAT, stochastic search-based methods, numerical methods for continuous optimization, dynamic programming, and applications to FPGA placement
Experience with NOC optimization for FPGA placement
Experience with applying machine learning techniques to EDA software
Job Type:
Regular
Shift:
Shift 1 (United States of America)
Primary Location:
San Jose, California, United States
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Similar Jobs (5)
Senior FPGA Compiler Software Engineer locations San Jose, California, United States time type Full time posted on Posted 12 Days Ago Principal FPGA Compiler Software Engineer locations San Jose, California, United States time type Full time posted on Posted 5 Days Ago FPGA Application Engineer PCIe locations San Jose, California, United States time type Full time posted on Posted 6 Days Ago Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Ourend-to-endbroad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet. Don't see the dream job you are looking for? Click " Get Started " below to drop off your contact information and resume and we will reach out to you if we find the perfect fit.
#J-18808-Ljbffr
Job Details:
Job Description:
Become a member of our world-class software research and development team! Altera develops programmable logic technologies to accelerate innovation for many customers worldwide. You will be designing and developing leading-edge software innovations for Quartus, the tool that optimizes our FPGA devices, within a research-oriented team. The Quartus Placement optimization engines are key to unlocking high performance, area and power efficiency for our customer's design applications. As part of the Quartus Placement team, your role will include: Actively researching & developing novel optimization algorithms for our FPGA CAD software tools, including timing-driven analytic placement, detailed placement, partitioning and floorplanning
Developing and optimizing the software to drive performance improvements by leveraging innovative FPGA hardware features
Ideal candidates exhibit the following behavioral traits: Intellectual curiosity and a passion for exploring new technology
Excellent problem-solving, debugging, and attention to detail
Great communication, teamwork, and interpersonal skills
Salary Range The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. $178.9k - $259.0k USD #LI-CG1 Qualifications:
Minimum Requirements: Degree in Electrical Engineering, Computer Engineering, Computer Science or related field.
MS + 10 years of industry software experience, or PhD + 5 years of industry software experience
Desired/Preferred Skills: Significant experience coding & hands-on development of high performance multi-core software systems
Extensive experience developing EDA placement optimization algorithms
Proven leadership skills for collaborative cross functional projects
Experience with Altera Quartus or AMD Vivado software
Experience with combinatorial/continuous optimization, including but not limited to Boolean SAT, stochastic search-based methods, numerical methods for continuous optimization, dynamic programming, and applications to FPGA placement
Experience with NOC optimization for FPGA placement
Experience with applying machine learning techniques to EDA software
Job Type:
Regular
Shift:
Shift 1 (United States of America)
Primary Location:
San Jose, California, United States
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Similar Jobs (5)
Senior FPGA Compiler Software Engineer locations San Jose, California, United States time type Full time posted on Posted 12 Days Ago Principal FPGA Compiler Software Engineer locations San Jose, California, United States time type Full time posted on Posted 5 Days Ago FPGA Application Engineer PCIe locations San Jose, California, United States time type Full time posted on Posted 6 Days Ago Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Ourend-to-endbroad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet. Don't see the dream job you are looking for? Click " Get Started " below to drop off your contact information and resume and we will reach out to you if we find the perfect fit.
#J-18808-Ljbffr