Design Verification Engineer

Tara Technical Solutions (TTS) provided pay range This range is provided by Tara Technical Solutions (TTS). Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

All the relevant skills, qualifications and experience that a successful applicant will need are listed in the following description. Base pay range $130,000.00/yr - $192,000.00/yr Direct message the job poster from Tara Technical Solutions (TTS) Tara Technical Solutions Recruiting- 24 Years of Semiconductor Recruiting. Functional verification of complex designs. Responsible for verification from test planning, test bench development, test execution and functional/code coverage closure. Skills/Expertise: Expertise in architecting reusable and constrained random test benches from scratch. Expertise in verification methodologies like UVM. Verification expertise with Interface IP designs. Beneficial areas would include High bandwidth memory (HBM) PHY / controller sub-systems, Ethernet/PCIE/CXL (Physical coding sublayer)/Serdes designs. Experience with ARM based bus protocols like APB, AXI and CHI is highly desirable. Strong understanding of System Verilog assertions and ability to quickly write effective coverage and assertion properties. Minimum Industry Experience : Bachelor's Degree + 8+ years of related experience; OR Master's Degree + 6+ years of experience. Having Exp in Memory Controllers And Or HBM or Ethernet/MAC is also a PLUS. * H1B Transfer IS NOT open at this time. Seniority level

Seniority levelMid-Senior level Employment type

Employment typeFull-time Job function

Job functionEngineering and Design IndustriesSemiconductor Manufacturing Referrals increase your chances of interviewing at Tara Technical Solutions (TTS) by 2x Inferred from the description for this job Medical insurance Vision insurance 401(k) Paid maternity leave Child care support Pension plan Paid paternity leave Student loan assistance Disability insurance Tuition assistance Get notified about new Design Verification Engineer jobs in

San Jose, CA . San Jose, CA $150,000.00-$230,000.00 1 day ago Santa Clara, CA $150,000.00-$260,000.00 5 days ago Santa Clara, CA $150,000.00-$250,000.00 1 day ago Cupertino, CA $129,800.00-$212,800.00 2 weeks ago Sunnyvale, CA $114,000.00-$166,000.00 2 weeks ago San Jose, CA $136,000.00-$204,000.00 2 days ago San Jose, CA $175,000.00-$225,000.00 1 day ago San Jose, CA $160,000.00-$240,000.00 1 day ago Sunnyvale, CA $114,000.00-$166,000.00 2 weeks ago San Jose, CA $180,000.00-$240,000.00 1 day ago Design Verification Engineer at Santa Clara, CA (Onsite) Menlo Park, CA $114,000.00-$166,000.00 5 hours ago Physical Design and Verification Engineer San Jose, CA $129,400.00-$177,900.00 1 day ago Sunnyvale, CA $142,000.00-$203,000.00 2 weeks ago San Jose, CA $140,000.00-$160,000.00 1 month ago Mountain View, CA $107,900.00-$242,000.00 1 week ago Santa Clara, CA $96,000.00-$184,000.00 3 days ago Sunnyvale, CA $173,000.00-$249,000.00 2 weeks ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.

#J-18808-Ljbffr