Design Verification Engineer - SoC Infrastructure

Join to apply for the Design Verification Engineer - SoC Infrastructure role at Prodapt

Join to apply for the Design Verification Engineer - SoC Infrastructure role at Prodapt

Overview
Prodapt is a global technology company and the largest specialized player in the Connectedness industry. As an AI-first strategic partner, Prodapt provides consulting, business transformation, and managed services to top telecom and tech enterprises.

Overview
Prodapt is a global technology company and the largest specialized player in the Connectedness industry. As an AI-first strategic partner, Prodapt provides consulting, business transformation, and managed services to top telecom and tech enterprises. Prodapt ASIC Services is a leading provider of SoC ASIC/FPGA and Embedded Software services . We offer turnkey solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design, UVM Verification, Emulation, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up. Our embedded services include firmware, device drivers, RTOS porting, and board bring-up . A“Great Place To WorkCertified” company, Prodapt employs over 6,000 technology and domain experts in 30+ countries. Prodapt is part of the 130-year-old business conglomerate
The Jhaver Group, which employs over 32,000 people across 80+ locations globally.
We're seeking a passionate Verification Engineer with a strong background in UVM-based verification and experience in working with complex ARM/RISC-based SOCs to join our dynamic team.
Looking for candidates in Mountain View, CA | El Segundo, CA | Austin, TX
Long term Contract
Responsibilities
As a Verification Engineer with expertise in subsystems and SoCs, you will be responsible for verifying the functional correctness of RTL for infrastructure SOCs. You'll collaborate closely with the project team to understand subsystem architecture, review design specifications, and develop a comprehensive verification strategy. Your key responsibilities will include planning verification activities, delivering high-quality SoC RTL within specified timelines, and leading the verification team in crafting test plans, developing testbenches, and debugging test failures.
Requirements

• Experience with SystemVerilog and verification methodologies (UVM)
• UVM From Scratch
• Solid understanding of digital hardware design and Verilog HDL.
• Detailed understanding and experience of current verification strategies for sophisticated SOC development, including software-based techniques.
• Good knowledge of test plan creation and tracking.
  
  

Nice To Have Skills & Experience:

• Experience with ARM-based designs and/or RISC-V-based SOC.
• Experience leading teams or projects.
• Experience or knowledge in clock domain crossing verification, power-aware verification, and development of complex SOCs on emulation platforms.
• Experience working with emulators and debugging complex SOC designs.

Seniority level

• Seniority level

  Entry level

Employment type

• Employment type

  Full-time

Job function

• Job function

  Engineering and Information Technology

• Industries

  Technology, Information and Internet

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