Samsung Semiconductor
Staff Engineer, CPU Design Verification
Samsung Semiconductor, San Jose, California, United States, 95199
Overview
Staff Engineer, CPU Design Verification at Samsung Semiconductor. Onsite in San Jose, CA. Job ID: 42637. ARL is part of SAIT, Samsung's R&D hub and incubator for cutting-edge technologies. SAIT's mission spans AI applications/algorithms, neuromorphic processing, domain-specific accelerators, new materials, quantum computing, and supercomputer systems. ARL is committed to shaping the future of CPU processors and SoC architecture for AI and HPC, building the foundation of processors and platforms used across Samsung's businesses. We are seeking an experienced CPU verification engineer to join our high-performance CPU design team. Location
Daily onsite presence at our San Jose office/headquarters in alignment with our Flexible Work policy. Responsibilities
Develop and execute verification strategy for CPU design at cluster/unit level. Architect and develop UVM-based cluster/unit level verification environments to verify functionality of CPU units. Develop detailed functional test plans, coverage monitors, and analyze coverage to continuously improve quality of design, testbench, and tests. Drive continuous improvement initiatives by evaluating new tools, methodologies, and technologies to increase effectiveness of pre-silicon verification. Work with architecture and design teams to align verification effort with overall project and organizational goals. Mentor and guide junior verification team members to foster a collaborative environment and build technical expertise. What You Bring
Bachelor's in Electrical/Computer Engineering with 10+ years of relevant industry experience, or Master's in Electrical/Computer Engineering with 8+ years, or PhD with 5+ years of experience (preferred). Proven experience in unit/cluster level verification of high-performance CPU units, including one of:
Out-of-order, superscalar instruction execution unit Memory subsystem (LSU, MMU, Data Cache hierarchy)
Experience with high-performance processor microarchitecture, and familiarity with digital logic design. Strong understanding of CPU architectures, instruction sets (x86, ARM, RISC-V). Experience with development of unit test environments: checkers, monitors, BFMs. Proficiency with SystemVerilog, UVM, SVA, and constrained-random test generation. Familiarity with simulators, understanding of best practices to avoid performance issues. Familiarity with Formal, Emulation, gate-level simulation and post-silicon debug experience is a plus. You're inclusive, adapting your style to the situation and diverse global norms of our people. An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. You're collaborative, building relationships, humbly offering support and openly welcoming approaches. Innovative and creative, you proactively explore new ideas and adapt quickly to change. Seniority level
Mid-Senior level Employment type
Full-time Job function
Engineering and Information Technology Industries
Semiconductor Manufacturing
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Staff Engineer, CPU Design Verification at Samsung Semiconductor. Onsite in San Jose, CA. Job ID: 42637. ARL is part of SAIT, Samsung's R&D hub and incubator for cutting-edge technologies. SAIT's mission spans AI applications/algorithms, neuromorphic processing, domain-specific accelerators, new materials, quantum computing, and supercomputer systems. ARL is committed to shaping the future of CPU processors and SoC architecture for AI and HPC, building the foundation of processors and platforms used across Samsung's businesses. We are seeking an experienced CPU verification engineer to join our high-performance CPU design team. Location
Daily onsite presence at our San Jose office/headquarters in alignment with our Flexible Work policy. Responsibilities
Develop and execute verification strategy for CPU design at cluster/unit level. Architect and develop UVM-based cluster/unit level verification environments to verify functionality of CPU units. Develop detailed functional test plans, coverage monitors, and analyze coverage to continuously improve quality of design, testbench, and tests. Drive continuous improvement initiatives by evaluating new tools, methodologies, and technologies to increase effectiveness of pre-silicon verification. Work with architecture and design teams to align verification effort with overall project and organizational goals. Mentor and guide junior verification team members to foster a collaborative environment and build technical expertise. What You Bring
Bachelor's in Electrical/Computer Engineering with 10+ years of relevant industry experience, or Master's in Electrical/Computer Engineering with 8+ years, or PhD with 5+ years of experience (preferred). Proven experience in unit/cluster level verification of high-performance CPU units, including one of:
Out-of-order, superscalar instruction execution unit Memory subsystem (LSU, MMU, Data Cache hierarchy)
Experience with high-performance processor microarchitecture, and familiarity with digital logic design. Strong understanding of CPU architectures, instruction sets (x86, ARM, RISC-V). Experience with development of unit test environments: checkers, monitors, BFMs. Proficiency with SystemVerilog, UVM, SVA, and constrained-random test generation. Familiarity with simulators, understanding of best practices to avoid performance issues. Familiarity with Formal, Emulation, gate-level simulation and post-silicon debug experience is a plus. You're inclusive, adapting your style to the situation and diverse global norms of our people. An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. You're collaborative, building relationships, humbly offering support and openly welcoming approaches. Innovative and creative, you proactively explore new ideas and adapt quickly to change. Seniority level
Mid-Senior level Employment type
Full-time Job function
Engineering and Information Technology Industries
Semiconductor Manufacturing
#J-18808-Ljbffr