Altera
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Silicon Design Verification Engineer
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Altera Join to apply for the
Silicon Design Verification Engineer
role at
Altera Get AI-powered advice on this job and more exclusive features. Performs functional logic verification of an IP and/or subsystem to ensure design will meet specification requirements. Develops FPGA IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the FPGA design and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with FPGA architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. May also collaborate with systems and software engineers to support integration testing of the FPGA. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Documents, reviews, and executes the verification strategy plan on different methodologies/techniques (e.g., gate-level-simulation strategy, power patterns/aware simulations) used to enable feature coverage as per the microarchitecture specifications.
Any additional information you require for this job can be found in the below text Make sure to read thoroughly, then apply.
Job Details
Job Description:
Performs functional logic verification of an IP and/or subsystem to ensure design will meet specification requirements. Develops FPGA IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the FPGA design and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with FPGA architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. May also collaborate with systems and software engineers to support integration testing of the FPGA. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Documents, reviews, and executes the verification strategy plan on different methodologies/techniques (e.g., gate-level-simulation strategy, power patterns/aware simulations) used to enable feature coverage as per the microarchitecture specifications.
Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$210k - $280k USD
Qualifications
BS in Electrical Engineering, Computer Science or related field. 8+ years of experience in design verification in IP or subsystem Demonstrated knowledge of System Verilog and UVM. Formal and emulation is a plus. Proven ability to have done the full verification lifecycle from testplans, environment ownership, coverage closure and bug tracking etc.
Job Type
Regular
Shift
Shift 1 (United States of America)
Primary Location:
San Jose, California, United States
Additional Locations:
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Seniority level
Seniority levelMid-Senior level Employment type
Employment typeFull-time Job function
Job functionEngineering and Information Technology IndustriesSemiconductor Manufacturing Referrals increase your chances of interviewing at Altera by 2x Sign in to set job alerts for “Design Verification Engineer” roles. Cupertino, CA $129,800.00-$212,800.00 2 weeks ago Sunnyvale, CA $114,000.00-$166,000.00 2 weeks ago San Jose, CA $136,000.00-$204,000.00 5 days ago Sunnyvale, CA $114,000.00-$166,000.00 2 weeks ago Design Verification Engineer at Santa Clara, CA (Onsite) Mountain View, CA $107,900.00-$242,000.00 3 weeks ago Physical Design and Verification Engineer Santa Clara, CA $97,700.00-$182,624.00 2 days ago Sunnyvale, CA $142,000.00-$203,000.00 2 weeks ago San Jose, CA $140,000.00-$160,000.00 1 month ago Mountain View, CA $107,900.00-$242,000.00 1 week ago Sunnyvale, CA $173,000.00-$249,000.00 2 weeks ago Santa Clara, CA $96,000.00-$184,000.00 6 days ago San Jose, CA $129,400.00-$177,900.00 4 days ago Advanced Physical Design and Verification Engineer (7036) San Jose, CA $85,500.00-$134,000.00 1 day ago ASIC Design Verification Engineer, Devices and Services Mountain View, CA $156,000.00-$229,000.00 15 hours ago San Jose, CA $130,000.00-$192,000.00 5 days ago Santa Clara, CA $161,250.00-$260,000.00 6 months ago San Jose, CA $150,000.00-$275,000.00 2 weeks ago Santa Clara, CA $108,000.00-$212,750.00 6 days ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
#J-18808-Ljbffr
Silicon Design Verification Engineer
role at
Altera Join to apply for the
Silicon Design Verification Engineer
role at
Altera Get AI-powered advice on this job and more exclusive features. Performs functional logic verification of an IP and/or subsystem to ensure design will meet specification requirements. Develops FPGA IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the FPGA design and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with FPGA architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. May also collaborate with systems and software engineers to support integration testing of the FPGA. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Documents, reviews, and executes the verification strategy plan on different methodologies/techniques (e.g., gate-level-simulation strategy, power patterns/aware simulations) used to enable feature coverage as per the microarchitecture specifications.
Any additional information you require for this job can be found in the below text Make sure to read thoroughly, then apply.
Job Details
Job Description:
Performs functional logic verification of an IP and/or subsystem to ensure design will meet specification requirements. Develops FPGA IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the FPGA design and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with FPGA architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. May also collaborate with systems and software engineers to support integration testing of the FPGA. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Documents, reviews, and executes the verification strategy plan on different methodologies/techniques (e.g., gate-level-simulation strategy, power patterns/aware simulations) used to enable feature coverage as per the microarchitecture specifications.
Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$210k - $280k USD
Qualifications
BS in Electrical Engineering, Computer Science or related field. 8+ years of experience in design verification in IP or subsystem Demonstrated knowledge of System Verilog and UVM. Formal and emulation is a plus. Proven ability to have done the full verification lifecycle from testplans, environment ownership, coverage closure and bug tracking etc.
Job Type
Regular
Shift
Shift 1 (United States of America)
Primary Location:
San Jose, California, United States
Additional Locations:
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Seniority level
Seniority levelMid-Senior level Employment type
Employment typeFull-time Job function
Job functionEngineering and Information Technology IndustriesSemiconductor Manufacturing Referrals increase your chances of interviewing at Altera by 2x Sign in to set job alerts for “Design Verification Engineer” roles. Cupertino, CA $129,800.00-$212,800.00 2 weeks ago Sunnyvale, CA $114,000.00-$166,000.00 2 weeks ago San Jose, CA $136,000.00-$204,000.00 5 days ago Sunnyvale, CA $114,000.00-$166,000.00 2 weeks ago Design Verification Engineer at Santa Clara, CA (Onsite) Mountain View, CA $107,900.00-$242,000.00 3 weeks ago Physical Design and Verification Engineer Santa Clara, CA $97,700.00-$182,624.00 2 days ago Sunnyvale, CA $142,000.00-$203,000.00 2 weeks ago San Jose, CA $140,000.00-$160,000.00 1 month ago Mountain View, CA $107,900.00-$242,000.00 1 week ago Sunnyvale, CA $173,000.00-$249,000.00 2 weeks ago Santa Clara, CA $96,000.00-$184,000.00 6 days ago San Jose, CA $129,400.00-$177,900.00 4 days ago Advanced Physical Design and Verification Engineer (7036) San Jose, CA $85,500.00-$134,000.00 1 day ago ASIC Design Verification Engineer, Devices and Services Mountain View, CA $156,000.00-$229,000.00 15 hours ago San Jose, CA $130,000.00-$192,000.00 5 days ago Santa Clara, CA $161,250.00-$260,000.00 6 months ago San Jose, CA $150,000.00-$275,000.00 2 weeks ago Santa Clara, CA $108,000.00-$212,750.00 6 days ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
#J-18808-Ljbffr