Celestial A
As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system’s interconnect bandwidth, memory bandwidth, and memory capacity. Celestial AI’s Photonic Fabric is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions.
The Photonic Fabric is available to our customers in multiple technology offerings, including optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.
This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact. To bolster customer collaborations, Celestial AI is developing a Photonic Fabric ecosystem consisting of tier-1 partnerships that include custom silicon/ASIC design, system integrators, HBM memory, assembly, and packaging suppliers.
ABOUT THE ROLE
We are seeking a highly motivated CAD Engineer to develop and maintain our EDA environments, design flows, and infrastructure for cutting-edge chip development. In this role, you will bridge Analog/AMS and ASIC/Digital Verification teams, ensuring seamless integration from schematic capture to signoff. You will own PDK integration, tool automation, cluster optimization, and mixed-signal verification flows while collaborating with designers, IT, and EDA vendors to accelerate our silicon success. ESSENTIAL DUTIES AND RESPONSIBILITIES
Develop and maintain CAD environments for Analog/AMS, ASIC, Photonics and Systems teams, ensuring seamless integration across the organization. Define, implement, and automate design and signoff flows for custom and digital. Install, configure, and optimize EDA tools (Cadence/Synopsys/Siemens) and FlexLM licenses. Integrate and validate PDKs, tech files and IP libraries, collaborating with foundry and third-party vendors. Manage SLURM cluster infrastructure, job scheduling, and resource allocation to maximize ROI. Write automation scripts (Python, TCL, SKILL, Bash) to accelerate CAD flows and reduce manual overhead. Maintain design repositories (IC Manage gdpxl for analog, Git for ASIC) and enforce version control best practices. Debug SPICE, DRC/LVS, PEX, and EMIR issues, working with designers to improve performance and reliability. Monitor license/cluster usage, analyze trends, and recommend cost-effective scaling strategies. Liaise with EDA vendors to resolve issues, drive tool improvements, and evaluate emerging solutions. QUALIFICATIONS
BS/MS in Electrical Engineering or Computer Science 10+ years of CAD/EDA design-automation experience supporting analog/AMS and preferably ASIC/DV teams Hands-on expertise with Cadence Virtuoso (schematic & layout), ADE Assembler/Explorer, Spectre Signoff experience with Pegasus, Quantus, and VoltusFI or equivalent Calibre toolsets Strong SKILL scripting and Python development skills for flow automation FlexLM license server installation, configuration, and troubleshooting IP Version control. Git, IC Manage (gdpxl) or equivalent PDK integration for TSMC FinFET nodes down to N5 PREFERRED QUALIFICATIONS
Experience with Virtuoso AMS Designer and Cadence Xcelium for behavioral modeling Experience with SLURM cluster manager Exposure to CI/CD pipelines for CAD-flow release and regression automation Strong written and verbal communication skills; proven mentorship of junior engineers LOCATION
Santa Clara, CA or Toronto, ON, Canada As an early stage start up, we offer an extremely attractive total compensation package inclusive of competitive base salary, bonus and a generous grant of our valuable early-stage equity. The target base salary for this role is approximately $175,000.00 - $215,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews. We offer great benefits (health, vision, dental and life insurance), collaborative and continuous learning work environment, where you will get a chance to work with smart and dedicated people engaged in developing the next generation architecture for high performance computing. Celestial AI Inc. is proud to be an equal opportunity workplace and is an affirmative action employer. Voluntary Self-Identification
For government reporting purposes, we ask candidates to respond to the below self-identification survey. Completion of the form is entirely voluntary. Whatever your decision, it will not be considered in the hiring process or thereafter. Any information that you do provide will be recorded and maintained in a confidential file. As set forth in Celestial AI’s Equal Employment Opportunity policy, we do not discriminate on the basis of any protected status under any applicable law. If you believe you belong to any of the categories of protected veterans listed below, please indicate by making the appropriate selection. As a government contractor subject to the Vietnam Era Veterans Readjustment Assistance Act (VEVRAA), we request this information to measure the effectiveness of the outreach and positive recruitment efforts we undertake pursuant to VEVRAA. A "disabled veteran" is one of the following: a veteran of the U.S. military, ground, naval or air service who is entitled to compensation (or who but for the receipt of military retired pay would be entitled to compensation) under laws administered by the Secretary of Veterans Affairs; or a person who was discharged or released from active duty because of a service-connected disability. A "recently separated veteran" means any veteran during the three-year period beginning on the date of such veteran's discharge or release from active duty in the U.S. military, ground, naval, or air service. An "active duty wartime or campaign badge veteran" means a veteran who served on active duty in the U.S. military, ground, naval or air service during a war, or in a campaign or expedition for which a campaign badge has been authorized under the laws administered by the Department of Defense. An "Armed forces service medal veteran" means a veteran who, while serving on active duty in the U.S. military, ground, naval or air service, participated in a United States military operation for which an Armed Forces service medal was awarded pursuant to Executive Order 12985. Disability Status Select... PUBLIC BURDEN STATEMENT: According to the Paperwork Reduction Act of 1995 no persons are required to respond to a collection of information unless such collection displays a valid OMB control number. This survey should take about 5 minutes to complete.
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We are seeking a highly motivated CAD Engineer to develop and maintain our EDA environments, design flows, and infrastructure for cutting-edge chip development. In this role, you will bridge Analog/AMS and ASIC/Digital Verification teams, ensuring seamless integration from schematic capture to signoff. You will own PDK integration, tool automation, cluster optimization, and mixed-signal verification flows while collaborating with designers, IT, and EDA vendors to accelerate our silicon success. ESSENTIAL DUTIES AND RESPONSIBILITIES
Develop and maintain CAD environments for Analog/AMS, ASIC, Photonics and Systems teams, ensuring seamless integration across the organization. Define, implement, and automate design and signoff flows for custom and digital. Install, configure, and optimize EDA tools (Cadence/Synopsys/Siemens) and FlexLM licenses. Integrate and validate PDKs, tech files and IP libraries, collaborating with foundry and third-party vendors. Manage SLURM cluster infrastructure, job scheduling, and resource allocation to maximize ROI. Write automation scripts (Python, TCL, SKILL, Bash) to accelerate CAD flows and reduce manual overhead. Maintain design repositories (IC Manage gdpxl for analog, Git for ASIC) and enforce version control best practices. Debug SPICE, DRC/LVS, PEX, and EMIR issues, working with designers to improve performance and reliability. Monitor license/cluster usage, analyze trends, and recommend cost-effective scaling strategies. Liaise with EDA vendors to resolve issues, drive tool improvements, and evaluate emerging solutions. QUALIFICATIONS
BS/MS in Electrical Engineering or Computer Science 10+ years of CAD/EDA design-automation experience supporting analog/AMS and preferably ASIC/DV teams Hands-on expertise with Cadence Virtuoso (schematic & layout), ADE Assembler/Explorer, Spectre Signoff experience with Pegasus, Quantus, and VoltusFI or equivalent Calibre toolsets Strong SKILL scripting and Python development skills for flow automation FlexLM license server installation, configuration, and troubleshooting IP Version control. Git, IC Manage (gdpxl) or equivalent PDK integration for TSMC FinFET nodes down to N5 PREFERRED QUALIFICATIONS
Experience with Virtuoso AMS Designer and Cadence Xcelium for behavioral modeling Experience with SLURM cluster manager Exposure to CI/CD pipelines for CAD-flow release and regression automation Strong written and verbal communication skills; proven mentorship of junior engineers LOCATION
Santa Clara, CA or Toronto, ON, Canada As an early stage start up, we offer an extremely attractive total compensation package inclusive of competitive base salary, bonus and a generous grant of our valuable early-stage equity. The target base salary for this role is approximately $175,000.00 - $215,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews. We offer great benefits (health, vision, dental and life insurance), collaborative and continuous learning work environment, where you will get a chance to work with smart and dedicated people engaged in developing the next generation architecture for high performance computing. Celestial AI Inc. is proud to be an equal opportunity workplace and is an affirmative action employer. Voluntary Self-Identification
For government reporting purposes, we ask candidates to respond to the below self-identification survey. Completion of the form is entirely voluntary. Whatever your decision, it will not be considered in the hiring process or thereafter. Any information that you do provide will be recorded and maintained in a confidential file. As set forth in Celestial AI’s Equal Employment Opportunity policy, we do not discriminate on the basis of any protected status under any applicable law. If you believe you belong to any of the categories of protected veterans listed below, please indicate by making the appropriate selection. As a government contractor subject to the Vietnam Era Veterans Readjustment Assistance Act (VEVRAA), we request this information to measure the effectiveness of the outreach and positive recruitment efforts we undertake pursuant to VEVRAA. A "disabled veteran" is one of the following: a veteran of the U.S. military, ground, naval or air service who is entitled to compensation (or who but for the receipt of military retired pay would be entitled to compensation) under laws administered by the Secretary of Veterans Affairs; or a person who was discharged or released from active duty because of a service-connected disability. A "recently separated veteran" means any veteran during the three-year period beginning on the date of such veteran's discharge or release from active duty in the U.S. military, ground, naval, or air service. An "active duty wartime or campaign badge veteran" means a veteran who served on active duty in the U.S. military, ground, naval or air service during a war, or in a campaign or expedition for which a campaign badge has been authorized under the laws administered by the Department of Defense. An "Armed forces service medal veteran" means a veteran who, while serving on active duty in the U.S. military, ground, naval or air service, participated in a United States military operation for which an Armed Forces service medal was awarded pursuant to Executive Order 12985. Disability Status Select... PUBLIC BURDEN STATEMENT: According to the Paperwork Reduction Act of 1995 no persons are required to respond to a collection of information unless such collection displays a valid OMB control number. This survey should take about 5 minutes to complete.
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