ASIC Verification Engineer

Responsibilities: Work closely with the design team to review and understand specifications / architectures / micro-architectures Define and review verification test plans Develop block level and chip level verification environments including testbenches, scoreboards, regressions, tools, infrastructure and methodology Produce functional / code coverage metrics Run regression and debug / triage failures in simulation environment Validate features and work with software teams to debug issues in the lab Requirements: BSEE with 3+ years or MSEE with 1+ years experience Advanced knowledge of standard ASIC/FPGA verification flows including simulation, testbench development, and post silicon bring-up and validation Excellent knowledge of System Verilog and Verilog Experience in developing test benches using the OVM, VMM or UVM methodology Good knowledge with C/C++ Experience with either Perl or Python scripts Knowledge of industry high speed interface standard protocols (PCI Express, DDR, NAND Flash etc.) strongly desired Experience in computer storage and networking is desired Team player with excellent communication skills and the desire to take on diverse challenges

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