Nutanix
Overview
Hit Apply below to send your application for consideration Ensure that your CV is up to date, and that you have read the job specs first. Company: Qualcomm Technologies, Inc.
Job Area: Engineering Group, ASICS Engineering
General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.
QCT's Digital ASIC Team is actively seeking candidates for several physical design engineering positions in our SOC and core design team. As a physical design engineer you will innovate, develop, and implement chips and cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power designs such as GPU, Camera and other MM, DDR, Modem, Audio. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction, performance, and power goals. Additional responsibilities include understanding functional and test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, cell placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for MMMC designs, implementing timing fixes and functional ECOs, debugging and fixing physical violations, and formal verification. The individual should have deep knowledge of scripting and software languages including Python, PERL/TCL, Linux/Unix shell and C. This individual will design, verify, and deliver complex Physical Design solutions from netlist and timing constraints to the final product.
Responsibilities
Innovate, develop, and implement chips and cores using state-of-the-art tools and technologies as part of a physical design team.
Own or contribute to the complete Physical Design Flow and deliveries of complex, high-speed, low power designs (GPU, Camera, MM, DDR, Modem, Audio).
Develop and enable low power implementation methods, customized place-and-route to achieve area reduction, performance, and power goals.
Understand and address functional and test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, cell placement, and MMMC clock tree synthesis.
Perform routing, timing optimization and closure, RC extraction, signal integrity, cross-talk noise and delay analysis; debug timing violations for MMMC designs and implement timing fixes and functional ECOs; fix physical violations and perform formal verification.
Demonstrate scripting and software skills (Python, Perl/TCL, Linux/Unix shell, C) to design, verify, and deliver Physical Design solutions from netlist to final product.
Preferred Qualifications
6+ years of industry experience in Physical Design, with expertise in Place & Route tools (Cadence Innovus and/or Synopsys Fusion Compiler).
Timing closure experience in Synopsys PTSI.
Formal verification experience.
Power domain analysis experience.
Physical verification experience.
Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Or Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
Or PhD in Science, Engineering, or related field.
EEO and Accommodations Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. You may email disability-accomodations@qualcomm.com. Qualcomm will provide reasonable accommodations to support individuals with disabilities to participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities.
Notice to Staffing and Recruiting Agencies Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Do not forward resumes to our jobs alias. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.
Pay range and Benefits Pay range: $115,600.00 - $173,400.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Salary is only one component of total compensation at Qualcomm. We offer a competitive annual discretionary bonus program and the opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). Our benefits package is designed to support success at work, at home, and at play. Your recruiter can discuss all that Qualcomm has to offer.
If you would like more information about this role, please contact Qualcomm Careers.
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Hit Apply below to send your application for consideration Ensure that your CV is up to date, and that you have read the job specs first. Company: Qualcomm Technologies, Inc.
Job Area: Engineering Group, ASICS Engineering
General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.
QCT's Digital ASIC Team is actively seeking candidates for several physical design engineering positions in our SOC and core design team. As a physical design engineer you will innovate, develop, and implement chips and cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power designs such as GPU, Camera and other MM, DDR, Modem, Audio. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction, performance, and power goals. Additional responsibilities include understanding functional and test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, cell placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for MMMC designs, implementing timing fixes and functional ECOs, debugging and fixing physical violations, and formal verification. The individual should have deep knowledge of scripting and software languages including Python, PERL/TCL, Linux/Unix shell and C. This individual will design, verify, and deliver complex Physical Design solutions from netlist and timing constraints to the final product.
Responsibilities
Innovate, develop, and implement chips and cores using state-of-the-art tools and technologies as part of a physical design team.
Own or contribute to the complete Physical Design Flow and deliveries of complex, high-speed, low power designs (GPU, Camera, MM, DDR, Modem, Audio).
Develop and enable low power implementation methods, customized place-and-route to achieve area reduction, performance, and power goals.
Understand and address functional and test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, cell placement, and MMMC clock tree synthesis.
Perform routing, timing optimization and closure, RC extraction, signal integrity, cross-talk noise and delay analysis; debug timing violations for MMMC designs and implement timing fixes and functional ECOs; fix physical violations and perform formal verification.
Demonstrate scripting and software skills (Python, Perl/TCL, Linux/Unix shell, C) to design, verify, and deliver Physical Design solutions from netlist to final product.
Preferred Qualifications
6+ years of industry experience in Physical Design, with expertise in Place & Route tools (Cadence Innovus and/or Synopsys Fusion Compiler).
Timing closure experience in Synopsys PTSI.
Formal verification experience.
Power domain analysis experience.
Physical verification experience.
Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Or Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
Or PhD in Science, Engineering, or related field.
EEO and Accommodations Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. You may email disability-accomodations@qualcomm.com. Qualcomm will provide reasonable accommodations to support individuals with disabilities to participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities.
Notice to Staffing and Recruiting Agencies Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Do not forward resumes to our jobs alias. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.
Pay range and Benefits Pay range: $115,600.00 - $173,400.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Salary is only one component of total compensation at Qualcomm. We offer a competitive annual discretionary bonus program and the opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). Our benefits package is designed to support success at work, at home, and at play. Your recruiter can discuss all that Qualcomm has to offer.
If you would like more information about this role, please contact Qualcomm Careers.
#J-18808-Ljbffr