Mulya Technologies
Principal layout design Engineer
Mulya Technologies, Milpitas, California, United States, 95035
Overview
We are leading provider of high-performance, ultra-low power IP cores and chips in advanced FinFET nodes, enabling differentiated system-on-chip (SoC) solutions. Our cutting-edge technology powers innovation across key markets such as 5G, wireline and optical communications, LiDAR, radar, automotive networking, AI, and image sensors. With a strong track record of success and over 50% year-over-year growth, We are at a pivotal moment—poised for rapid expansion and ready to further solidify its position as a technology leader. Location:
Milpitas, California, United States Senior layout designer
will be responsible for leading our layout activity for high performance analog cores such as analog-to-digital converters, PLL, transceivers etc. Responsibilities include leading IC layout of cutting edge high performance, high speed CMOS integrated circuits in foundry CMOS process nodes in 5nm, 6nm, 7nm, 16nm, and 28nm following best practices from the industry. This person will be responsible for establishing the layout procedures and practices within the company while helping to build up the layout team. The person will work in Milpitas, California, United States. Job requirements include the following qualifications. Responsibilities
No separate responsibilities section provided beyond the above description. The role entails leading layout activities for high-performance analog cores and establishing layout procedures. Qualifications
Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys. Must be able to set up LVS, DRC, ERC environments and debug verification issues using Cadence and Mentor tools. Experience with layout of high performance analog blocks such as analog to digital converters, references, digital to analog converters, PLL etc. desired. Experience with floor planning, block level routing and top level chip assembly. Knowledge of high performance analog layout techniques such as common centroid layout, shielding, use of dummy devices, thermal aware layout with consideration for electromigration. Demonstrated experience with analog layout for silicon chips in mass production. Experience with deep sub-micron design in foundry CMOS nodes 28nm and below preferred. Experience working with distributed design teams a plus. Knowledge of skill code an layout automation a plus. Self starter with the ability to define and adhere to a schedule. Must possess strong written and verbal communication skills. 10+ years experience in high performance analog layout in advanced CMOS process. We value
We are looking for trailblazers ... We strongly believe that the pace of the ongoing hardware revolution will be greatly accelerated by our IP cores and Automation. In the rapidly emerging semiconductor embedded design business ecosystem. We have created an exciting environment with amazing talent across multiple disciplines. We like self-motivated individuals, we encourage initiative, we look for leadership qualities, we value teamwork, we like diversity, and we reward excellence. We are looking for trailblazers to bring our vision to fruition. If you are interested in making an impact as part of a young, fast-growing, cutting-edge technology company, please reach out to us. We are an equal opportunity employer. We offer excellent compensation. We seek individuals that share our high standards and commitment to excellence. "Mining the Knowledge Community" Details
Seniority level
Mid-Senior level
Employment type
Full-time
Job function
Marketing, Sales, and Management
Industries
Semiconductor Manufacturing, Computer Hardware Manufacturing, and Appliances, Electrical, and Electronics Manufacturing
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We are leading provider of high-performance, ultra-low power IP cores and chips in advanced FinFET nodes, enabling differentiated system-on-chip (SoC) solutions. Our cutting-edge technology powers innovation across key markets such as 5G, wireline and optical communications, LiDAR, radar, automotive networking, AI, and image sensors. With a strong track record of success and over 50% year-over-year growth, We are at a pivotal moment—poised for rapid expansion and ready to further solidify its position as a technology leader. Location:
Milpitas, California, United States Senior layout designer
will be responsible for leading our layout activity for high performance analog cores such as analog-to-digital converters, PLL, transceivers etc. Responsibilities include leading IC layout of cutting edge high performance, high speed CMOS integrated circuits in foundry CMOS process nodes in 5nm, 6nm, 7nm, 16nm, and 28nm following best practices from the industry. This person will be responsible for establishing the layout procedures and practices within the company while helping to build up the layout team. The person will work in Milpitas, California, United States. Job requirements include the following qualifications. Responsibilities
No separate responsibilities section provided beyond the above description. The role entails leading layout activities for high-performance analog cores and establishing layout procedures. Qualifications
Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys. Must be able to set up LVS, DRC, ERC environments and debug verification issues using Cadence and Mentor tools. Experience with layout of high performance analog blocks such as analog to digital converters, references, digital to analog converters, PLL etc. desired. Experience with floor planning, block level routing and top level chip assembly. Knowledge of high performance analog layout techniques such as common centroid layout, shielding, use of dummy devices, thermal aware layout with consideration for electromigration. Demonstrated experience with analog layout for silicon chips in mass production. Experience with deep sub-micron design in foundry CMOS nodes 28nm and below preferred. Experience working with distributed design teams a plus. Knowledge of skill code an layout automation a plus. Self starter with the ability to define and adhere to a schedule. Must possess strong written and verbal communication skills. 10+ years experience in high performance analog layout in advanced CMOS process. We value
We are looking for trailblazers ... We strongly believe that the pace of the ongoing hardware revolution will be greatly accelerated by our IP cores and Automation. In the rapidly emerging semiconductor embedded design business ecosystem. We have created an exciting environment with amazing talent across multiple disciplines. We like self-motivated individuals, we encourage initiative, we look for leadership qualities, we value teamwork, we like diversity, and we reward excellence. We are looking for trailblazers to bring our vision to fruition. If you are interested in making an impact as part of a young, fast-growing, cutting-edge technology company, please reach out to us. We are an equal opportunity employer. We offer excellent compensation. We seek individuals that share our high standards and commitment to excellence. "Mining the Knowledge Community" Details
Seniority level
Mid-Senior level
Employment type
Full-time
Job function
Marketing, Sales, and Management
Industries
Semiconductor Manufacturing, Computer Hardware Manufacturing, and Appliances, Electrical, and Electronics Manufacturing
We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
#J-18808-Ljbffr