Viridan Group
Overview
My client, a leading semiconductor innovator, is seeking a Senior RTL Design Engineer to join their team developing next-generation low-power SoCs. This role is ideal for an experienced digital design engineer who enjoys building complex architectures, driving quality, and collaborating across disciplines to bring cutting-edge products to life.
What You’ll Do
Contribute to architecture and micro-architecture development for digital SoC modules and ensure their quality prior to tape-out.
Implement and optimize RTL designs in Verilog for IP and SoC integration.
Evaluate and integrate third-party IPs, ensuring seamless functionality within SoC designs.
Partner with verification teams to develop test plans, debug issues, and support validation on FPGA platforms.
Work closely with physical design engineers to achieve timing closure and meet performance/power requirements.
Run quality checks such as Lint, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) and drive fixes as needed.
Participate in silicon bring-up, validation, and debugging efforts post-tape-out.
What We’re Looking For
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
8+ years of experience in ASIC/SoC digital design with a focus on RTL development.
Strong proficiency in Verilog/SystemVerilog and hands-on experience with large-scale SoC projects.
Familiarity with FPGA bring-up, verification environments, and physical design handoff.
Solid understanding of timing, power, and area trade-offs in SoC design.
Experience running design quality checks (Lint, CDC, RDC) and working across functions to resolve issues.
Excellent problem-solving, communication, and collaboration skills.
Why Join?
Opportunity to contribute to industry-leading low-power semiconductor solutions.
Collaborative and fast-paced team environment.
Competitive compensation and benefits package.
Growth potential with a company driving innovation in next-gen SoC technology.
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What You’ll Do
Contribute to architecture and micro-architecture development for digital SoC modules and ensure their quality prior to tape-out.
Implement and optimize RTL designs in Verilog for IP and SoC integration.
Evaluate and integrate third-party IPs, ensuring seamless functionality within SoC designs.
Partner with verification teams to develop test plans, debug issues, and support validation on FPGA platforms.
Work closely with physical design engineers to achieve timing closure and meet performance/power requirements.
Run quality checks such as Lint, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) and drive fixes as needed.
Participate in silicon bring-up, validation, and debugging efforts post-tape-out.
What We’re Looking For
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
8+ years of experience in ASIC/SoC digital design with a focus on RTL development.
Strong proficiency in Verilog/SystemVerilog and hands-on experience with large-scale SoC projects.
Familiarity with FPGA bring-up, verification environments, and physical design handoff.
Solid understanding of timing, power, and area trade-offs in SoC design.
Experience running design quality checks (Lint, CDC, RDC) and working across functions to resolve issues.
Excellent problem-solving, communication, and collaboration skills.
Why Join?
Opportunity to contribute to industry-leading low-power semiconductor solutions.
Collaborative and fast-paced team environment.
Competitive compensation and benefits package.
Growth potential with a company driving innovation in next-gen SoC technology.
#J-18808-Ljbffr