Infobahn Softworld Inc
ASIC/RTL Design Verification Engineer
Infobahn Softworld Inc, Santa Clara, California, us, 95053
Get AI-powered advice on this job and more exclusive features.
Direct message the job poster from Infobahn Softworld Inc
Account Delivery Manager at Infobahn Softworld Inc
Work Location:
Santa Clara, CA (2-3 days in Office per week) THE ROLE: We are looking for an adaptive, self-motivative Design Verification Engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs. KEY RESPONSIBILITIES: Develop/Maintain tests for functional verification. Build the directed and random verification tests, debug test failures to determine the root cause, work with RTL and firmware engineers to resolve design defects and correct any test issues. Work on functional & code coverage verification. Provide technical support to other teams PREFERRED EXPERIENCE: Experience with C/C++ Experience with Verilog, System Verilog, and modern verification libraries like UVM 10+years of ASIC design verification experience Experience / Background with DDR or Memory Controller. PHY Verification is a plus Experience with scripting languages like Python, Perl and TCL is a plus. Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Understanding of Design for Test methodologies and DFT verification experience is a plus Proficient in debugging firmware and RTL code using simulation tools ACADEMIC CREDENTIALS: Bachelor’s or master’s degree in computer engineering/Electrical Engineering Seniority level
Mid-Senior level Employment type
Contract Job function
Engineering and Information Technology Industries
Computers and Electronics Manufacturing and Software Development
#J-18808-Ljbffr
Work Location:
Santa Clara, CA (2-3 days in Office per week) THE ROLE: We are looking for an adaptive, self-motivative Design Verification Engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs. KEY RESPONSIBILITIES: Develop/Maintain tests for functional verification. Build the directed and random verification tests, debug test failures to determine the root cause, work with RTL and firmware engineers to resolve design defects and correct any test issues. Work on functional & code coverage verification. Provide technical support to other teams PREFERRED EXPERIENCE: Experience with C/C++ Experience with Verilog, System Verilog, and modern verification libraries like UVM 10+years of ASIC design verification experience Experience / Background with DDR or Memory Controller. PHY Verification is a plus Experience with scripting languages like Python, Perl and TCL is a plus. Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Understanding of Design for Test methodologies and DFT verification experience is a plus Proficient in debugging firmware and RTL code using simulation tools ACADEMIC CREDENTIALS: Bachelor’s or master’s degree in computer engineering/Electrical Engineering Seniority level
Mid-Senior level Employment type
Contract Job function
Engineering and Information Technology Industries
Computers and Electronics Manufacturing and Software Development
#J-18808-Ljbffr